Inventor · disambiguated record
Igor Ermolaev
Also filed as: ERMOLAEV IGOR
11 granted patents·4 pending applications·41 citations·filing 2008–2022
87Inventor score
Top patents by PatentIndex Score
15 records- 0193US10191744B2Apparatuses, methods, and systems for element sorting of vectorsINTEL CORP·Filed 2016·Granted Jan 29, 2019·14 cites·24 claims
- 0280US9218182B2Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)ERMOLAEV IGOR·Filed 2012·Granted Dec 22, 2015·7 cites·20 claims
- 0377US9122475B2Instruction for shifting bits left with pulling ones into less significant bitsPLOTNIKOV MIKHAIL·Filed 2012·Granted Sep 1, 2015·5 cites·20 claims
- 0475US9552205B2Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructionsINTEL CORP·Filed 2013·Granted Jan 24, 2017·3 cites·25 claims
- 0572US10929133B2Apparatuses, methods, and systems for element sorting of vectorsINTEL CORP·Filed 2019·Granted Feb 23, 2021·1 cites·24 claims
- 0672US8347038B2Optimizing memory copy routine selection for message passing in a multicore architectureINTEL CORP·Filed 2008·Granted Jan 1, 2013·7 cites·19 claims
- 0771US9910670B2Instruction set for eliminating misaligned memory accesses during processing of an array having misaligned data rowsINTEL CORP·Filed 2014·Granted Mar 6, 2018·3 cites·22 claims
- 0859US8700857B2Optimizing memory copy routine selection for message passing in a multicore architectureINTEL CORP·Filed 2012·Granted Apr 15, 2014·1 cites·20 claims
- 0953US9684510B2Systems, apparatuses, and methods for performing a shuffle and operation (Shuffle-Op)INTEL CORP·Filed 2015·Granted Jun 20, 2017·0 cites·20 claims
- 1049US10884750B2Strideshift instruction for transposing bits inside vector registerINTEL CORP·Filed 2017·Granted Jan 5, 2021·0 cites·21 claims
- 1145US2024004662A1Instructions and support for horizontal reductionsINTEL CORP·Filed 2022·Application pending·0 cites
- 1245US2017329609A1Apparatus and method for performing a spin-loop jumpINTEL CORP·Filed 2014·Application pending·0 cites
- 1343US10838720B2Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectorsINTEL CORP·Filed 2016·Granted Nov 17, 2020·0 cites·25 claims
- 1439US2019347101A1Vector compress2 and expand2 instructions with two memory locationsINTEL CORP·Filed 2017·Application pending·0 cites
- 1536US2017192789A1Systems, Methods, and Apparatuses for Improving Vector ThroughputMALLADI RAMA KISHNAN V·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →