Inventor · disambiguated record
Igor Peidous
Also filed as: PEIDOUS IGOR · PEIDOUS IGOR V
71 granted patents·5 pending applications·1,169 citations·filing 1997–2025
99Inventor score
Files withGLOBALWAFERS CO LTD18CHARTERED SEMICONDUCTOR MFG17ADVANCED MICRO DEVICES INC15SUNEDISON SEMICONDUCTOR LTD UEN201334164H10SUNEDISON SEMICONDUCTOR LTD3
Top patents by PatentIndex Score
76 records- 0199US5989978AShallow trench isolation of MOSFETS with reduced corner parasitic currentsCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Nov 23, 1999·393 cites·22 claims
- 0297US7534689B2Stress enhanced MOS transistor and methods for its fabricationADVANCED MICRO DEVICES INC·Filed 2006·Granted May 19, 2009·74 cites·20 claims
- 0396US7410859B1Stressed MOS device and method for its fabricationADVANCED MICRO DEVICES INC·Filed 2005·Granted Aug 12, 2008·61 cites·16 claims
- 0493US9831115B2Process flow for manufacturing semiconductor on insulator structures in parallelSUNEDISON SEMICONDUCTOR LTD (UEN201334164H)·Filed 2017·Granted Nov 28, 2017·10 cites·23 claims
- 0593US6180490B1Method of filling shallow trenchesCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jan 30, 2001·174 cites·11 claims
- 0692US11081386B2High resistivity SOI wafers and a method of manufacturing thereofGLOBALWAFERS CO LTD·Filed 2020·Granted Aug 3, 2021·2 cites·22 claims
- 0792US10283402B2Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stressSUNEDISON SEMICONDUCTOR LTD UEN201334164H·Filed 2016·Granted May 7, 2019·6 cites·60 claims
- 0891US10468294B2High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surfaceSUNEDISON SEMICONDUCTOR LTD·Filed 2017·Granted Nov 5, 2019·8 cites·30 claims
- 0989US11142844B2High resistivity single crystal silicon ingot and wafer having improved mechanical strengthGLOBALWAFERS CO LTD·Filed 2017·Granted Oct 12, 2021·5 cites·45 claims
- 1088US11081407B2Methods for assessing semiconductor structuresGLOBALWAFERS CO LTD·Filed 2019·Granted Aug 3, 2021·4 cites·6 claims
- 1188US7767540B2Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobilityADVANCED MICRO DEVICES INC·Filed 2006·Granted Aug 3, 2010·11 cites·11 claims
- 1288US7348233B1Methods for fabricating a CMOS device including silicide contactsADVANCED MICRO DEVICES INC·Filed 2005·Granted Mar 25, 2008·17 cites·16 claims
- 1387US7902008B2Methods for fabricating a stressed MOS deviceGLOBALFOUNDRIES INC·Filed 2005·Granted Mar 8, 2011·13 cites·14 claims
- 1487US7462524B1Methods for fabricating a stressed MOS deviceADVANCED MICRO DEVICES INC·Filed 2005·Granted Dec 9, 2008·15 cites·7 claims
- 1586US2025259884A1High resistivity silicon-on-insulator substrate comprising an isolation regionGLOBALWAFERS CO LTD·Filed 2025·Application pending·0 cites
- 1684US12300535B2High resistivity silicon-on-insulator substrate comprising an isolation regionGLOBALWAFERS CO LTD·Filed 2023·Granted May 13, 2025·0 cites·13 claims
- 1783US10910257B2High resistivity SOI wafers and a method of manufacturing thereofGLOBALWAFERS CO LTD·Filed 2018·Granted Feb 2, 2021·2 cites·16 claims
- 1882US10622247B2Semiconductor on insulator structure comprising a buried high resistivity layerSUNEDISON SEMICONDUCTOR LTD·Filed 2017·Granted Apr 14, 2020·3 cites·28 claims
- 1982US10083855B2Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si depositionSUNEDISON SEMICONDUCTOR LTD UEN201334164H·Filed 2017·Granted Sep 25, 2018·3 cites·30 claims
- 2081US11508612B2Semiconductor on insulator structure comprising a buried high resistivity layerGLOBALWAFERS CO LTD·Filed 2019·Granted Nov 22, 2022·2 cites·10 claims
- 2181US10079170B2High resistivity SOI wafers and a method of manufacturing thereofSUNEDISON SEMICONDUCTOR LTD·Filed 2014·Granted Sep 18, 2018·3 cites·62 claims
- 2280US7326601B2Methods for fabrication of a stressed MOS deviceADVANCED MICRO DEVICES INC·Filed 2005·Granted Feb 5, 2008·9 cites·17 claims
- 2378US8802522B2Methods to adjust threshold voltage in semiconductor devicesWARD MICHAEL G·Filed 2011·Granted Aug 12, 2014·7 cites·20 claims
- 2478US8039878B2Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobilityADVANCED MICRO DEVICES INC·Filed 2010·Granted Oct 18, 2011·3 cites·19 claims
- 2578US5930646AMethod of shallow trench isolationCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Jul 27, 1999·62 cites·12 claims
- 2677US7605045B2Field effect transistors and methods for fabricating the sameADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 20, 2009·7 cites·17 claims
- 2777US7456058B1Stressed MOS device and methods for its fabricationADVANCED MICRO DEVICES INC·Filed 2005·Granted Nov 25, 2008·6 cites·4 claims
- 2877US6027982AMethod to form shallow trench isolation structures with improved isolation fill and surface planarityCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Feb 22, 2000·57 cites·20 claims
- 2977US5937297AMethod for making sub-quarter-micron MOSFETCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Aug 10, 1999·34 cites·27 claims
- 3075US11587825B2Method of preparing an isolation region in a high resistivity silicon-on-insulator substrateGLOBALWAFERS CO LTD·Filed 2020·Granted Feb 21, 2023·0 cites·16 claims
- 3175US11380576B2Method of preparing an isolation region in a high resistivity silicon-on-insulator substrateGLOBALWAFERS CO LTD·Filed 2020·Granted Jul 5, 2022·0 cites·16 claims
- 3275US7494918B2Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereofIBM·Filed 2006·Granted Feb 24, 2009·6 cites·7 claims
- 3374US11594446B2High resistivity SOI wafers and a method of manufacturing thereofGLOBALWAFERS CO LTD·Filed 2021·Granted Feb 28, 2023·0 cites·22 claims
- 3472US11655560B2High resistivity single crystal silicon ingot and wafer having improved mechanical strengthGLOBALWAFERS CO LTD·Filed 2021·Granted May 23, 2023·0 cites·30 claims
- 3572US11655559B2High resistivity single crystal silicon ingot and wafer having improved mechanical strengthGLOBALWAFERS CO LTD·Filed 2021·Granted May 23, 2023·0 cites·27 claims
- 3672US8143138B2Method for fabricating interconnect structures for semiconductor devicesPATZ RYAN JAMES·Filed 2008·Granted Mar 27, 2012·6 cites·6 claims
- 3770US11699615B2High resistivity semiconductor-on-insulator wafer and a method of manufactureGLOBALWAFERS CO LTD·Filed 2021·Granted Jul 11, 2023·0 cites·11 claims
- 3870US6249035B1LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effectCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 19, 2001·17 cites·3 claims
- 3967US10825718B2Method of preparing an isolation region in a high resistivity silicon-on-insulator substrateGLOBALWAFERS CO LTD·Filed 2019·Granted Nov 3, 2020·0 cites·22 claims
- 4066US10483152B2High resistivity semiconductor-on-insulator wafer and a method of manufacturingSUNEDISON SEMICONDUCTOR LTD UEN201334164H·Filed 2015·Granted Nov 19, 2019·1 cites·28 claims
- 4165US10784146B2Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stressGLOBALWAFERS CO LTD·Filed 2019·Granted Sep 22, 2020·0 cites·16 claims
- 4265US7696534B2Stressed MOS deviceADVANCED MICRO DEVICES INC·Filed 2008·Granted Apr 13, 2010·2 cites·14 claims
- 4365US6049107ASub-quarter-micron MOSFET and method of its manufacturingCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Apr 11, 2000·20 cites·10 claims
- 4464US10475695B2High resistivity silicon-on-insulator substrate comprising an isolation regionSUNEDISON SEMICONDUCTOR LTD UEN201334164H·Filed 2018·Granted Nov 12, 2019·0 cites·16 claims
- 4564US9768056B2Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si depositionSUNEDISON SEMICONDUCTOR LTD (UEN201334164H)·Filed 2014·Granted Sep 19, 2017·1 cites·57 claims
- 4663US10381260B2Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layersSUNEDISON SEMICONDUCTOR LTD UEN201334164H·Filed 2015·Granted Aug 13, 2019·1 cites·18 claims
- 4763US7704840B2Stress enhanced transistor and methods for its fabricationADVANCED MICRO DEVICES INC·Filed 2006·Granted Apr 27, 2010·2 cites·18 claims
- 4862US10269617B2High resistivity silicon-on-insulator substrate comprising an isolation regionSUNEDISON SEMICONDUCTOR LTD UEN201334164H·Filed 2017·Granted Apr 23, 2019·0 cites·17 claims
- 4962US7754554B2Methods for fabricating low contact resistance CMOS circuitsGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 13, 2010·1 cites·19 claims
- 5061US10658227B2Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stressGLOBALWAFERS CO LTD·Filed 2018·Granted May 19, 2020·0 cites·56 claims
Showing the top 50 of 76 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →