Inventor · disambiguated record
Ilyas Elkin
Also filed as: ELKIN ILYAS
21 granted patents·3 pending applications·90 citations·filing 2004–2023
93Inventor score
Top patents by PatentIndex Score
24 records- 0194US8890573B2Clock gating latch, method of operation thereof and integrated circuit employing the sameELKIN ILYAS·Filed 2012·Granted Nov 18, 2014·19 cites·20 claims
- 0292US9667230B1Latch and flip-flop circuits with shared clock-enabled supply nodesNVIDIA CORP·Filed 2016·Granted May 30, 2017·14 cites·20 claims
- 0385US9448125B2Determining on-chip voltage and temperatureSINGH ABHISHEK·Filed 2012·Granted Sep 20, 2016·8 cites·20 claims
- 0485US9071233B2Low power master-slave flip-flopNVIDIA CORP·Filed 2013·Granted Jun 30, 2015·6 cites·5 claims
- 0581US8659337B2Latch circuit with a bridging deviceELKIN ILYAS·Filed 2011·Granted Feb 25, 2014·5 cites·12 claims
- 0678US10466968B1Radix-4 multiplier partial product generation with improved area and powerNVIDIA CORP·Filed 2018·Granted Nov 5, 2019·2 cites·16 claims
- 0778US7164302B1One gate delay output noise insensitive latchSUN MICROSYSTEMS INC·Filed 2004·Granted Jan 16, 2007·21 cites·8 claims
- 0868US9077329B2Latch circuit with a bridging deviceNVIDIA CORP·Filed 2014·Granted Jul 7, 2015·2 cites·15 claims
- 0967US8035425B2Active echo on-die repeater circuitORACLE AMERICA INC·Filed 2008·Granted Oct 11, 2011·3 cites·20 claims
- 1067US7890826B2Method and apparatus for test of asynchronous pipelinesORACLE AMERICA INC·Filed 2006·Granted Feb 15, 2011·5 cites·16 claims
- 1165US9435861B2Efficient scan latch systems and methodsNVIDIA CORP·Filed 2012·Granted Sep 6, 2016·1 cites·14 claims
- 1262US9438213B2Low power master-slave flip-flopNVIDIA CORP·Filed 2015·Granted Sep 6, 2016·1 cites·10 claims
- 1360US10120028B2Efficient scan latch systems and methodsNVIDIA CORP·Filed 2016·Granted Nov 6, 2018·0 cites·18 claims
- 1460US7629815B1Low-power semi-dynamic flip-flop with smart keeperSUN MICROSYSTEMS INC·Filed 2008·Granted Dec 8, 2009·3 cites·12 claims
- 1559US11294631B2Full adder cell with improved power efficiencyNVIDIA CORP·Filed 2019·Granted Apr 5, 2022·0 cites·20 claims
- 1658US12387028B2Data path circuit design using reinforcement learningNVIDIA CORP·Filed 2021·Granted Aug 12, 2025·0 cites·20 claims
- 1758US11169779B2Full adder cell with improved power efficiencyNVIDIA CORP·Filed 2020·Granted Nov 9, 2021·0 cites·19 claims
- 1853US2024160406A1Low-precision floating-point datapath in a computer processorNVIDIA CORP·Filed 2023·Application pending·0 cites
- 1947US2023100785A1Priority encoder-based techniques for computing the minimum or the maximum of multiple valuesNVIDIA CORP·Filed 2021·Application pending·0 cites
- 2044US10931266B2Low power flip-flop element with gated clockNVIDIA CORP·Filed 2014·Granted Feb 23, 2021·0 cites·22 claims
- 2141US8952705B2System and method for examining asymetric operationsELKIN ILYAS·Filed 2011·Granted Feb 10, 2015·0 cites·20 claims
- 2238US9496853B2Via resistance analysis systems and methodsPOPPE WOJCIECH JAKUB·Filed 2012·Granted Nov 15, 2016·0 cites·20 claims
- 2334US9425772B2Coupling resistance and capacitance analysis systems and methodsPOPPE WOJCIECH JAKUB·Filed 2012·Granted Aug 23, 2016·0 cites·19 claims
- 2430US2013106524A1System and method for examining leakage impactsELKIN ILYAS·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →