Inventor · disambiguated record
Ish Chadha
Also filed as: CHADHA ISH
15 granted patents·7 pending applications·20 citations·filing 2017–2025
88Inventor score
Files withNVIDIA CORP22
Top patents by PatentIndex Score
22 records- 0195US11569939B1Synchronizing a high-speed signaling interconnectNVIDIA CORP·Filed 2021·Granted Jan 31, 2023·8 cites·20 claims
- 0291US11784890B2Link training through handshake on high-speed interconnectNVIDIA CORP·Filed 2021·Granted Oct 10, 2023·4 cites·20 claims
- 0390US11956342B2Reliable link management for a high-speed signaling interconnectNVIDIA CORP·Filed 2022·Granted Apr 9, 2024·2 cites·20 claims
- 0486US11575494B1Link status detection for a high-speed signaling interconnectNVIDIA CORP·Filed 2021·Granted Feb 7, 2023·2 cites·20 claims
- 0583US11936379B2Digital delay line calibration with duty cycle correction for high bandwidth memory interfaceNVIDIA CORP·Filed 2022·Granted Mar 19, 2024·1 cites·20 claims
- 0682US2025348107A1High-speed signaling system with ground referenced signaling (grs) over substrateNVIDIA CORP·Filed 2025·Application pending·0 cites
- 0781US2025385777A1Reliable link management for a high-speed signaling interconnectNVIDIA CORP·Filed 2025·Application pending·0 cites
- 0877US10317459B2Multi-chip package with selection logic and debug ports for testing inter-chip communicationsNVIDIA CORP·Filed 2017·Granted Jun 11, 2019·3 cites·15 claims
- 0976US12443555B2Frame alignment recovery for a high-speed signaling interconnectNVIDIA CORP·Filed 2023·Granted Oct 14, 2025·0 cites·20 claims
- 1075US12395311B2Reliable link management for a high-speed signaling interconnectNVIDIA CORP·Filed 2024·Granted Aug 19, 2025·0 cites·20 claims
- 1174US12353271B2Error rate interrupts in hardware for high-speed signaling interconnectNVIDIA CORP·Filed 2023·Granted Jul 8, 2025·0 cites·20 claims
- 1273US12405629B2High-speed signaling system with ground referenced signaling (GRS) over substrateNVIDIA CORP·Filed 2022·Granted Sep 2, 2025·0 cites·20 claims
- 1370US12477398B2Method and system for transmitting in-band cross-chip triggers to maintain high-speed interconnectNVIDIA CORP·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 1467US11899609B2Frame alignment recovery for a high-speed signaling interconnectNVIDIA CORP·Filed 2021·Granted Feb 13, 2024·0 cites·20 claims
- 1563US11880265B2Error rate interrupts in hardware for high-speed signaling interconnectNVIDIA CORP·Filed 2021·Granted Jan 23, 2024·0 cites·18 claims
- 1658US12027198B2Mitigating duty cycle distortion degradation due to device aging on high-bandwidth memory interfaceNVIDIA CORP·Filed 2022·Granted Jul 2, 2024·0 cites·20 claims
- 1757US12461880B2Test data transfer in multi-die systemsNVIDIA CORP·Filed 2024·Granted Nov 4, 2025·0 cites·25 claims
- 1855US2025328484A1Low-power frame transmission over a communication interconnectNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1954US2025300827A1Synchronizing an encrypted data stream across chip-to-chip ground referenced signaling interconnectNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2054US2025370951A1Configuring and debugging a die-to-die link using a sideband linkNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2153US2025358091A1Die-to-die interface using simultaneous bidirectional links on an interposerNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2252US2025298432A1Transmitter-side link training with in-band handshakingNVIDIA CORP·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →