Inventor · disambiguated record
Ismed D. Hartanto
Also filed as: HARTANTO ISMED D · HARTANTO ISMED D S
9 granted patents·1 pending application·96 citations·filing 2001–2020
88Inventor score
Top patents by PatentIndex Score
10 records- 0194US10234505B1Clock generation for integrated circuit testingXILINX INC·Filed 2017·Granted Mar 19, 2019·19 cites·20 claims
- 0291US7761755B1Circuit for and method of testing for faults in a programmable logic deviceXILINX INC·Filed 2007·Granted Jul 20, 2010·25 cites·20 claims
- 0389US8890562B1At-speed testing of multi-die integrated circuitsHARTANTO ISMED D·Filed 2011·Granted Nov 18, 2014·12 cites·14 claims
- 0486US7958414B1Enhancing security of internal memoryXILINX INC·Filed 2010·Granted Jun 7, 2011·10 cites·20 claims
- 0585US8311762B1Manufacturing test for a programmable integrated circuit implementing a specific user designHARTANTO ISMED D·Filed 2010·Granted Nov 13, 2012·7 cites·17 claims
- 0684US11386020B1Programmable device having a data processing engine (DPE) arrayXILINX INC·Filed 2020·Granted Jul 12, 2022·2 cites·21 claims
- 0782US9600018B1Clock stoppage in integrated circuits with multiple asynchronous clock domainsXILINX INC·Filed 2014·Granted Mar 21, 2017·7 cites·16 claims
- 0880US10969433B1Method to compress responses of automatic test pattern generation (ATPG) vectors into an on-chip multiple-input shift register (MISR)XILINX INC·Filed 2019·Granted Apr 6, 2021·7 cites·20 claims
- 0953US7062427B2Batch editor for netlists described in a hardware description languageWALTHER JOHN STEPHEN·Filed 2001·Granted Jun 13, 2006·7 cites·19 claims
- 1034US2005278593A1Scan-test structure having increased effectiveness and related systems and methodsMURADALI FIDEL·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →