Inventor · disambiguated record
Ishai Naveh
Also filed as: NAVEH ISHAI
15 granted patents·1 pending application·132 citations·filing 2008–2019
93Inventor score
Files withADESTO TECHNOLOGIES CORP6TOWER SEMICONDUCTOR LTD3ADESTO TECH CORP2DERHACOBIAN NARBEH2GILBERT NAD EDWARD2
Top patents by PatentIndex Score
16 records- 0197US8687403B1Circuits having programmable impedance elementsDERHACOBIAN NARBEH·Filed 2011·Granted Apr 1, 2014·31 cites·19 claims
- 0295US7948020B2Asymmetric single poly NMOS non-volatile memory cellTOWER SEMICONDUCTOR LTD·Filed 2010·Granted May 24, 2011·20 cites·20 claims
- 0394US7800156B2Asymmetric single poly NMOS non-volatile memory cellTOWER SEMICONDUCTOR LTD·Filed 2008·Granted Sep 21, 2010·30 cites·17 claims
- 0490US8947913B1Circuits and methods having programmable impedance elementsDERHACOBIAN NARBEH·Filed 2011·Granted Feb 3, 2015·15 cites·36 claims
- 0587US8913444B1Read operations and circuits for memory devices having programmable elements, including programmable resistance elementsGILBERT NAD EDWARD·Filed 2012·Granted Dec 16, 2014·10 cites·29 claims
- 0687US8675396B1Integrated circuit devices and systems having programmable impedance elements with different response typesADESTO TECHNOLOGIES CORP·Filed 2012·Granted Mar 18, 2014·7 cites·23 claims
- 0783US9812183B2Read latency reduction in a memory deviceADESTO TECH CORP·Filed 2016·Granted Nov 7, 2017·5 cites·6 claims
- 0879US10726888B2Read latency reduction in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2019·Granted Jul 28, 2020·3 cites·20 claims
- 0977US10290334B2Read latency reduction in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2017·Granted May 14, 2019·3 cites·20 claims
- 1074US10984861B1Reference circuits and methods for resistive memoriesADESTO TECHNOLOGIES CORP·Filed 2018·Granted Apr 20, 2021·3 cites·11 claims
- 1168US9343667B1Circuits having programmable impedance elements and vertical access devicesADESTO TECHNOLOGIES CORP·Filed 2014·Granted May 17, 2016·2 cites·9 claims
- 1263US9755142B1Methods of making memory devices with programmable impedance elements and vertically formed access devicesADESTO TECH CORP·Filed 2016·Granted Sep 5, 2017·1 cites·9 claims
- 1357US9570166B1Read operations and circuits for memory devices having programmable elements, including programmable resistance elementsGILBERT NAD EDWARD·Filed 2014·Granted Feb 14, 2017·1 cites·20 claims
- 1453US8902631B2Memory devices, circuits and, methods that apply different electrical conditions in access operationsSUNKAVALLI RAVI·Filed 2012·Granted Dec 2, 2014·1 cites·20 claims
- 1552US2010027346A1Asymmetric Single Poly NMOS Non-Volatile Memory CellTOWER SEMICONDUCTOR LTD·Filed 2009·Application pending·0 cites
- 1647US9373398B1Prototyping integrated circuit devices with programmable impedance elementsADESTO TECHNOLOGIES CORP·Filed 2015·Granted Jun 21, 2016·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →