Inventor · disambiguated record
Ivana Djurdjevic
Also filed as: DJURDJEVIC IVANA
19 granted patents·142 citations·filing 2006–2023
94Inventor score
Files withSEAGATE TECHNOLOGY LLC7LSI CORP4HITACHI GLOBAL STORAGE TECH NL2WESTERN DIGITAL TECH INC2GALBRAITH RICHARD LEO1
Top patents by PatentIndex Score
19 records- 0195US10177787B1Mitigation of error correction failure due to trapping setsSEAGATE TECHNOLOGY LLC·Filed 2015·Granted Jan 8, 2019·18 cites·18 claims
- 0294US8037394B2Techniques for generating bit reliability information in a post-processor using an error correction constraintHITACHI GLOBAL STORAGE TECH NL·Filed 2007·Granted Oct 11, 2011·38 cites·20 claims
- 0392US7814398B2Communication channel with Reed-Solomon encoding and single parity checkSEAGATE TECHNOLOGY LLC·Filed 2006·Granted Oct 12, 2010·18 cites·20 claims
- 0485US11233528B1Method and apparatus for LDPC decoding using indexed messagesSEAGATE TECHNOLOGY LLC·Filed 2020·Granted Jan 25, 2022·2 cites·20 claims
- 0584US10263640B2Low density parity check (LDPC) decoder with pre-saturation compensationSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Apr 16, 2019·6 cites·19 claims
- 0684US9513982B1Methods and systems for reducing decoder error floor for an electronic non-volatile computer storage apparatusLSI CORP·Filed 2014·Granted Dec 6, 2016·7 cites·20 claims
- 0784US9319073B2Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decodingSEAGATE TECHNOLOGY LLC·Filed 2014·Granted Apr 19, 2016·7 cites·20 claims
- 0881US8213229B2Error control in a flash memory deviceWILSON BRUCE A·Filed 2008·Granted Jul 3, 2012·14 cites·22 claims
- 0978US9037945B2Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoderLSI CORP·Filed 2013·Granted May 19, 2015·7 cites·20 claims
- 1077US8209578B2Systems using low density parity check codes for correcting errorsGALBRAITH RICHARD LEO·Filed 2008·Granted Jun 26, 2012·3 cites·21 claims
- 1176US8037393B2Techniques for generating bit reliability information in the post processorHITACHI GLOBAL STORAGE TECH NL·Filed 2007·Granted Oct 11, 2011·6 cites·20 claims
- 1275US8970976B1Systems and methods for data dependent inter-track interference cancellationLSI CORP·Filed 2013·Granted Mar 3, 2015·3 cites·20 claims
- 1373US10666295B1Mitigation of error correction failure due to trapping setsSEAGATE TECHNOLOGY LLC·Filed 2018·Granted May 26, 2020·2 cites·20 claims
- 1467US8341506B2Techniques for correcting errors using iterative decodingLI ZONGWANG·Filed 2007·Granted Dec 25, 2012·6 cites·20 claims
- 1564US9354816B2Read policy for system data of solid state drivesSEAGATE TECHNOLOGY LLC·Filed 2014·Granted May 31, 2016·1 cites·20 claims
- 1664US8650464B1Symmetric diagonal interleaving and encoding/decoding circuit and methodTONG PO·Filed 2011·Granted Feb 11, 2014·4 cites·17 claims
- 1763US12450119B2Minimizing redundancy for stuck bit codingWESTERN DIGITAL TECH INC·Filed 2023·Granted Oct 21, 2025·0 cites·19 claims
- 1858US12362029B2Stuck bits encoding and decoding on a storage deviceWESTERN DIGITAL TECH INC·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 1950US8861113B2Noise predictive filter adaptation for inter-track interference cancellationLSI CORP·Filed 2013·Granted Oct 14, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →