Inventor · disambiguated record
Ivan Pavisic
Also filed as: PAVISIC IVAN
55 granted patents·1 pending application·2,212 citations·filing 1996–2012
99Inventor score
Top patents by PatentIndex Score
56 records- 0198US7093228B2Method and system for classifying an integrated circuit for optical proximity correctionLSI LOGIC CORP·Filed 2002·Granted Aug 15, 2006·221 cites·27 claims
- 0296US6182272B1Metal layer assignmentLSI LOGIC CORP·Filed 1998·Granted Jan 30, 2001·332 cites·32 claims
- 0391US6292929B2Advanced modular cell placement systemLSI LOGIC CORP·Filed 1999·Granted Sep 18, 2001·142 cites·22 claims
- 0490US6550045B1Changing clock delays in an integrated circuit for skew optimizationLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·88 cites·16 claims
- 0590US6067409AAdvanced modular cell placement systemLSI LOGIC CORP·Filed 1997·Granted May 23, 2000·153 cites·23 claims
- 0689US6550044B1Method in integrating clock tree synthesis and timing optimization for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Apr 15, 2003·59 cites·9 claims
- 0787US6546541B1Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitancesLSI LOGIC CORP·Filed 2001·Granted Apr 8, 2003·52 cites·20 claims
- 0887US6412102B1Wire routing optimizationLSI LOGIC CORP·Filed 1998·Granted Jun 25, 2002·139 cites·33 claims
- 0987US5898597AIntegrated circuit floor plan optimization systemLSI LOGIC CORP·Filed 1997·Granted Apr 27, 1999·133 cites·20 claims
- 1086US6123736AMethod and apparatus for horizontal congestion removalLSI LOGIC CORP·Filed 1997·Granted Sep 26, 2000·119 cites·44 claims
- 1185US6068662AMethod and apparatus for congestion removalLSI LOGIG CORP·Filed 1997·Granted May 30, 2000·129 cites·29 claims
- 1285US6058254AMethod and apparatus for vertical congestion removalLSI LOGIC CORP·Filed 1997·Granted May 2, 2000·118 cites·37 claims
- 1384US7356785B2Optimizing IC clock structures by minimizing clock uncertaintyLSI LOGIC CORP·Filed 2006·Granted Apr 8, 2008·11 cites·5 claims
- 1482US8516425B2Method and computer program for generating grounded shielding wires for signal wiringNIKITIN ANDREY·Filed 2012·Granted Aug 20, 2013·7 cites·25 claims
- 1581US9024657B2Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smallerEASIC CORP·Filed 2012·Granted May 5, 2015·9 cites·18 claims
- 1680US6941533B2Clock tree synthesis with skew for memory devicesLSI LOGIC CORP·Filed 2002·Granted Sep 6, 2005·28 cites·22 claims
- 1780US6546539B1Netlist resynthesis program using structure co-factoringLSI LOGIC CORP·Filed 2000·Granted Apr 8, 2003·39 cites·8 claims
- 1879US6637016B1Assignment of cell coordinatesLSI LOGIC CORP·Filed 2001·Granted Oct 21, 2003·27 cites·13 claims
- 1979US6070108AMethod and apparatus for congestion driven placementLSI LOGIC CORP·Filed 1997·Granted May 30, 2000·84 cites·16 claims
- 2077US6487697B1Distribution dependent clustering in buffer insertion of high fanout netsLSI LOGIC CORP·Filed 2001·Granted Nov 26, 2002·24 cites·21 claims
- 2176US7818703B2Density driven layout for RRAM configuration moduleLSI CORP·Filed 2007·Granted Oct 19, 2010·6 cites·14 claims
- 2275US7996804B2Signal delay skew reduction systemLSI CORP·Filed 2008·Granted Aug 9, 2011·6 cites·15 claims
- 2375US7096442B2Optimizing IC clock structures by minimizing clock uncertaintyLSI LOGIC CORP·Filed 2003·Granted Aug 22, 2006·18 cites·14 claims
- 2471US6629304B1Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cellsLSI LOGIC CORP·Filed 2001·Granted Sep 30, 2003·16 cites·25 claims
- 2571US6557144B1Netlist resynthesis program based on physical delay calculationLSI LOGIC CORP·Filed 2000·Granted Apr 29, 2003·16 cites·7 claims
- 2667US6810515B2Process of restructuring logics in ICs for setup and hold time optimizationLSI LOGIC CORP·Filed 2002·Granted Oct 26, 2004·12 cites·18 claims
- 2767US6701493B2Floor plan tester for integrated circuit designLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·12 cites·14 claims
- 2864US6470487B1Parallelization of resynthesisLSI LOGIC CORP·Filed 2001·Granted Oct 22, 2002·10 cites·9 claims
- 2961US8239813B2Method and apparatus for balancing signal delay skewNIKITIN ANDREY·Filed 2011·Granted Aug 7, 2012·1 cites·17 claims
- 3061US7243324B2Method of buffer insertion to achieve pin specific delaysLSI CORP·Filed 2005·Granted Jul 10, 2007·2 cites·18 claims
- 3160US6757881B2Power routing with obstaclesLSI LOGIC CORP·Filed 2002·Granted Jun 29, 2004·7 cites·27 claims
- 3259US7194717B2Compact custom layout for RRAM column controllerLSI LOGIC CORP·Filed 2004·Granted Mar 20, 2007·10 cites·27 claims
- 3359US6760896B2Process layout of buffer modules in integrated circuitsLSI LOGIC CORP·Filed 2002·Granted Jul 6, 2004·6 cites·14 claims
- 3458US6526553B1Chip core size estimationLSI LOGIC CORP·Filed 2001·Granted Feb 25, 2003·5 cites·20 claims
- 3557US7667494B2Methods and apparatus for fast unbalanced pipeline architectureLSI CORP·Filed 2008·Granted Feb 23, 2010·1 cites·20 claims
- 3657US7246337B2Density driven layout for RRAM configuration moduleLSI CORP·Filed 2004·Granted Jul 17, 2007·4 cites·9 claims
- 3757US7028274B1RRAM backend flowLSI LOGIC CORP·Filed 2005·Granted Apr 11, 2006·1 cites·6 claims
- 3857US6463572B1IC timing analysis with known false pathsLSI LOGIC CORP·Filed 2001·Granted Oct 8, 2002·5 cites·19 claims
- 3957US6038385APhysical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimizationLSI LOGIC CORP·Filed 1996·Granted Mar 14, 2000·31 cites·46 claims
- 4053US6757877B2System and method for identifying and eliminating bottlenecks in integrated circuit designsLSI LOGIC CORP·Filed 2002·Granted Jun 29, 2004·7 cites·14 claims
- 4152US6553551B1Timing recomputationLSI LOGIC CORP·Filed 2001·Granted Apr 22, 2003·2 cites·11 claims
- 4252US6269469B1Method and apparatus for parallel routing locking mechanismLSI LOGIC CORP·Filed 1998·Granted Jul 31, 2001·25 cites·22 claims
- 4351US5796625APhysical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimizationLSI LOGIC CORP·Filed 1996·Granted Aug 18, 1998·23 cites·28 claims
- 4449US6804811B2Process for layout of memory matrices in integrated circuitsLSI LOGIC CORP·Filed 2002·Granted Oct 12, 2004·5 cites·22 claims
- 4549US6615397B1Optimal clock timing schedule for an integrated circuitLSI LOGIC CORP·Filed 2001·Granted Sep 2, 2003·2 cites·16 claims
- 4647US7207026B2Memory tiling architectureLSI LOGIC CORP·Filed 2004·Granted Apr 17, 2007·0 cites·4 claims
- 4746US7546505B2Built in self test transport controller architectureLSI CORP·Filed 2006·Granted Jun 9, 2009·1 cites·4 claims
- 4846US7334204B2System for avoiding false path pessimism in estimating net delay for an integrated circuit designLSI LOGIC CORP·Filed 2005·Granted Feb 19, 2008·0 cites·8 claims
- 4944US6000038AParallel processing of Integrated circuit pin arrival timesLSI LOGIC CORP·Filed 1997·Granted Dec 7, 1999·15 cites·11 claims
- 5042US6075933AMethod and apparatus for continuous column density optimizationLSI LOGIC CORP·Filed 1997·Granted Jun 13, 2000·13 cites·19 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →