Inventor · disambiguated record
Iwen Chao
Also filed as: CHAO IWEN
10 granted patents·2 pending applications·48 citations·filing 2004–2015
85Inventor score
Top patents by PatentIndex Score
12 records- 0185US9418000B2Dynamically compensating for degradation of a non-volatile memory deviceINTEL CORP·Filed 2014·Granted Aug 16, 2016·9 cites·21 claims
- 0278US7145249B2Semiconducting device with folded interposerINTEL CORP·Filed 2004·Granted Dec 5, 2006·25 cites·16 claims
- 0364US9543019B2Error corrected pre-read for upper page write in a multi-level cell memoryINTEL CORP·Filed 2012·Granted Jan 10, 2017·3 cites·13 claims
- 0462US7378725B2Semiconducting device with stacked diceINTEL CORP·Filed 2004·Granted May 27, 2008·10 cites·14 claims
- 0551US9236136B2Lower page read for multi-level cell memoryINTEL CORP·Filed 2012·Granted Jan 12, 2016·0 cites·19 claims
- 0651US8400831B2Method and apparatus for improving endurance of flash memoriesCHO HOON·Filed 2010·Granted Mar 19, 2013·1 cites·16 claims
- 0750US7741155B2Method of manufacturing semiconducting device with stacked diceINTEL CORP·Filed 2008·Granted Jun 22, 2010·0 cites·9 claims
- 0847US7482698B2Semiconducting device with folded interposerINTEL CORP·Filed 2006·Granted Jan 27, 2009·0 cites·15 claims
- 0947US7456048B2Semiconducting device with folded interposerINTEL CORP·Filed 2006·Granted Nov 25, 2008·0 cites·15 claims
- 1041US9524774B2Lower page read for multi-level cell memoryINTEL CORP·Filed 2015·Granted Dec 20, 2016·0 cites·18 claims
- 1135US2005179111A1Semiconductor device with low resistive path barrierFiled 2004·Application pending·0 cites
- 1233US2013339603A1Method, apparatus and system for determining access to a memory arrayZHU FENG·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →