Inventor · disambiguated record
Jais Abraham
Also filed as: ABRAHAM JAIS
10 granted patents·83 citations·filing 2002–2024
87Inventor score
Top patents by PatentIndex Score
10 records- 0189US7404126B2Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputsTEXAS INSTRUMENTS INC·Filed 2006·Granted Jul 22, 2008·20 cites·17 claims
- 0287US10656203B1Low pin count test controllerQUALCOMM INC·Filed 2019·Granted May 19, 2020·7 cites·20 claims
- 0386US7352169B2Testing components of I/O paths of an integrated circuitTEXAS INSTRUMENTS INC·Filed 2006·Granted Apr 1, 2008·21 cites·10 claims
- 0482US11935606B2Memory with scan chain testing of column redundancy logic and multiplexingQUALCOMM INC·Filed 2021·Granted Mar 19, 2024·1 cites·17 claims
- 0574US12327599B2Memory with scan chain testing of column redundancy logic and multiplexingQUALCOMM INC·Filed 2024·Granted Jun 10, 2025·0 cites·14 claims
- 0674US6853212B2Gated scan output flip-flopTEXAS INSTRUMENTS INC·Filed 2002·Granted Feb 8, 2005·23 cites·14 claims
- 0773US10996267B2Time interleaved scan systemQUALCOMM INC·Filed 2019·Granted May 4, 2021·1 cites·18 claims
- 0859US7421634B2Sequential scan based techniques to test interface between modules designed to operate at different frequenciesTEXAS INSTRUMENTS INC·Filed 2005·Granted Sep 2, 2008·4 cites·12 claims
- 0941US7082558B2Increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysisTEXAS INSTRUMENTS INC·Filed 2002·Granted Jul 25, 2006·6 cites·20 claims
- 1031US6981190B2Controlling the content of specific desired memory elements when testing integrated circuits using sequential scanning techniquesTEXAS INSTRUMENTS INC·Filed 2002·Granted Dec 27, 2005·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →