Inventor · disambiguated record
Jayachandra B. Avula
Also filed as: AVULA JAYACHANDRA · AVULA JAYACHANDRA B
3 granted patents·1 pending application·376 citations·filing 1994–2013
80Inventor score
Top patents by PatentIndex Score
4 records- 0188US5488729ACentral processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and executionROSS TECHNOLOGY INC·Filed 1994·Granted Jan 30, 1996·156 cites·7 claims
- 0284US5884060AProcessor which performs dynamic instruction scheduling at time of execution within a single clock cycleROSS TECHNOLOGY INC·Filed 1997·Granted Mar 16, 1999·127 cites·15 claims
- 0379US5640588ACPU architecture performing dynamic instruction scheduling at time of execution within single clock cycleROSS TECHNOLOGY INC·Filed 1996·Granted Jun 17, 1997·93 cites·8 claims
- 0436US2015139249A1System and Method for DebuggingEMULEX CORP·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →