Inventor · disambiguated record

Janusz K. Balicki

Also filed as: BALICKI JANUSZ · BALICKI JANUSZ K

7 granted patents·587 citations·filing 1993–2001

89Inventor score

Technology areasH03K

Files withALTERA CORP7

Top patents by PatentIndex Score

7 records

0195US5970255ASystem for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordinglyALTERA CORP·Filed 1995·Granted Oct 19, 1999·241 cites·34 claims
0295US5473266AProgrammable logic device having fast programmable logic array blocks and a central global interconnect arrayALTERA CORP·Filed 1994·Granted Dec 5, 1995·119 cites·12 claims
0393US5399922AMacrocell comprised of two look-up tables and two flip-flopsALTERA CORP·Filed 1993·Granted Mar 21, 1995·86 cites·9 claims
0491US5341044AFlexible configuration logic array block for programmable logic devicesALTERA CORP·Filed 1993·Granted Aug 23, 1994·71 cites·21 claims
0588US5953537AMethod and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic deviceALTERA CORP·Filed 1994·Granted Sep 14, 1999·61 cites·13 claims
0648US5523706AHigh speed, low power macrocellALTERA CORP·Filed 1995·Granted Jun 4, 1996·9 cites·9 claims
0733USRE40011ESystem for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordinglyALTERA CORP·Filed 2001·Granted Jan 22, 2008·0 cites·73 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →