Inventor · disambiguated record
Javed S. Barkatullah
Also filed as: BARKATULLAH JAVED · BARKATULLAH JAVED S · BARKATULLAH JAVED SABIR
30 granted patents·2 pending applications·1,038 citations·filing 1995–2019
98Inventor score
Top patents by PatentIndex Score
32 records- 0198US7015741B2Adaptive body bias for clock skew compensationINTEL CORP·Filed 2003·Granted Mar 21, 2006·134 cites·23 claims
- 0296US6922111B2Adaptive frequency clock signalINTEL CORP·Filed 2002·Granted Jul 26, 2005·67 cites·52 claims
- 0394US7133751B2Method and apparatus for detecting on-die voltage variationsINTEL CORP·Filed 2005·Granted Nov 7, 2006·25 cites·5 claims
- 0494US6882238B2Method and apparatus for detecting on-die voltage variationsINTEL CORP·Filed 2003·Granted Apr 19, 2005·60 cites·17 claims
- 0594US6208180B1Core clock correction in a 2/N mode clocking schemeINTEL CORP·Filed 1998·Granted Mar 27, 2001·181 cites·15 claims
- 0692US6611920B1Clock distribution system for selectively enabling clock signals to portions of a pipelined circuitINTEL CORP·Filed 2000·Granted Aug 26, 2003·88 cites·38 claims
- 0791US6622255B1Digital clock skew detection and phase alignmentINTEL CORP·Filed 2000·Granted Sep 16, 2003·50 cites·18 claims
- 0889US10250864B2Method and apparatus for generating enhanced 3D-effects for real-time and offline applicationsVEFXI CORP·Filed 2017·Granted Apr 2, 2019·5 cites·15 claims
- 0989US6750689B2Method and apparatus for correcting a clock duty cycle in a clock distribution networkINTEL CORP·Filed 2001·Granted Jun 15, 2004·32 cites·17 claims
- 1086US7042259B2Adaptive frequency clock generation systemINTEL CORP·Filed 2004·Granted May 9, 2006·34 cites·30 claims
- 1185US7562316B2Apparatus for power consumption reductionINTEL CORP·Filed 2006·Granted Jul 14, 2009·12 cites·20 claims
- 1283US7282966B2Frequency management apparatus, systems, and methodsINTEL CORP·Filed 2004·Granted Oct 16, 2007·34 cites·25 claims
- 1383US6268749B1Core clock correction in a 2/n mode clocking schemeINTEL CORP·Filed 2000·Granted Jul 31, 2001·28 cites·21 claims
- 1482US6704892B1Automated clock alignment for testing processors in a bypass modeINTEL CORP·Filed 2000·Granted Mar 9, 2004·26 cites·4 claims
- 1581US7342426B2PLL with controlled VCO biasINTEL CORP·Filed 2005·Granted Mar 11, 2008·10 cites·11 claims
- 1681US6192092B1Method and apparatus for clock skew compensationINTEL CORP·Filed 1998·Granted Feb 20, 2001·135 cites·18 claims
- 1775US10657065B2Delayed write-back in memoryEVERSPIN TECHNOLOGIES INC·Filed 2019·Granted May 19, 2020·1 cites·20 claims
- 1873US10268591B2Delayed write-back in memoryEVERSPIN TECHNOLOGIES INC·Filed 2018·Granted Apr 23, 2019·2 cites·20 claims
- 1972US7102402B2Circuit to manage and lower clock inaccuracies of integrated circuitsINTEL CORP·Filed 2002·Granted Sep 5, 2006·17 cites·14 claims
- 2071US9990300B2Delayed write-back in memoryEVERSPIN TECHNOLOGIES INC·Filed 2016·Granted Jun 5, 2018·2 cites·19 claims
- 2170US6934872B2Method and apparatus for optimizing clock distribution to reduce the effect of power supply noiseINTEL CORP·Filed 2001·Granted Aug 23, 2005·15 cites·21 claims
- 2269US6922112B2Clock signal generation and distribution via ring oscillatorsINTEL CORP·Filed 2002·Granted Jul 26, 2005·13 cites·48 claims
- 2366US5706485AMethod and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock featureINTEL CORP·Filed 1995·Granted Jan 6, 1998·30 cites·23 claims
- 2461US6629255B1Generating a 2-phase clock using a non-50% divider circuitINTEL CORP·Filed 2000·Granted Sep 30, 2003·7 cites·15 claims
- 2559US7096433B2Method for power consumption reductionINTEL CORP·Filed 2003·Granted Aug 22, 2006·5 cites·24 claims
- 2659US2015116458A1Method and apparatus for generating enhanced 3d-effects for real-time and offline appplicationsBARKATECH CONSULTING LLC·Filed 2014·Application pending·0 cites
- 2750US9967546B2Method and apparatus for converting 2D-images and videos to 3D for consumer, commercial and professional applicationsVEFXI CORP·Filed 2014·Granted May 8, 2018·0 cites·16 claims
- 2843US6104219AMethod and apparatus for generating 2/N mode bus clock signalsINTEL CORP·Filed 1998·Granted Aug 15, 2000·13 cites·17 claims
- 2942US5834956ACore clock correction in a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Nov 10, 1998·11 cites·12 claims
- 3041US7009437B2Smart buffer circuit to match a delay over a range of loadsINTEL CORP·Filed 2004·Granted Mar 7, 2006·1 cites·10 claims
- 3136US2007238434A1Clock modulation circuits with time averagingKURD NASSER·Filed 2006·Application pending·0 cites
- 3230US5821784AMethod and apparatus for generating 2/N mode bus clock signalsINTEL CORP·Filed 1996·Granted Oct 13, 1998·0 cites·42 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →