Inventor · disambiguated record
Jatin Bhartia
Also filed as: BHARTIA JATIN
17 granted patents·1 pending application·32 citations·filing 2014–2024
90Inventor score
Top patents by PatentIndex Score
18 records- 0191US9606805B1Accuracy of operand store compare prediction using confidence counterIBM·Filed 2015·Granted Mar 28, 2017·7 cites·17 claims
- 0290US9495156B1Accuracy of operand store compare prediction using confidence counterIBM·Filed 2016·Granted Nov 15, 2016·6 cites·1 claims
- 0388US9684550B2Robust and adaptable management of event countersIBM·Filed 2016·Granted Jun 20, 2017·5 cites·1 claims
- 0487US9594566B1Accuracy of operand store compare prediction using confidence counterIBM·Filed 2016·Granted Mar 14, 2017·4 cites·1 claims
- 0583US9858128B2Robust and adaptable management of event countersIBM·Filed 2016·Granted Jan 2, 2018·3 cites·1 claims
- 0678US9727395B2Robust and adaptable management of event countersIBM·Filed 2015·Granted Aug 8, 2017·2 cites·20 claims
- 0778US9547495B1Pattern based branch predictionIBM·Filed 2016·Granted Jan 17, 2017·2 cites·1 claims
- 0875US10216552B2Robust and adaptable management of event countersIBM·Filed 2017·Granted Feb 26, 2019·1 cites·17 claims
- 0962US12277070B2Cache line subscriptionADVANCED RISC MACH LTD·Filed 2023·Granted Apr 15, 2025·0 cites·19 claims
- 1062US9304883B2Testing optimization of microprocessor table functionsIBM·Filed 2014·Granted Apr 5, 2016·2 cites·7 claims
- 1160US11579889B2Programmable instruction buffering for accumulating a burst of instructionsADVANCED RISC MACH LTD·Filed 2020·Granted Feb 14, 2023·0 cites·18 claims
- 1256US10866810B2Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory addressADVANCED RISC MACH LTD·Filed 2018·Granted Dec 15, 2020·0 cites·18 claims
- 1355US9733946B2Pattern based branch predictionIBM·Filed 2016·Granted Aug 15, 2017·0 cites·1 claims
- 1453US9934041B2Pattern based branch predictionIBM·Filed 2015·Granted Apr 3, 2018·0 cites·20 claims
- 1548US11861368B2Re-enabling use of prediction table after execution state switchADVANCED RISC MACH LTD·Filed 2022·Granted Jan 2, 2024·0 cites·18 claims
- 1645US11775305B2Speculative usage of parallel decode unitsADVANCED RISC MACH LTD·Filed 2021·Granted Oct 3, 2023·0 cites·20 claims
- 1744US9760462B2Testing optimization of microprocessor table functionsIBM·Filed 2014·Granted Sep 12, 2017·0 cites·13 claims
- 1844US2025245010A1Return address restorationADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →