Inventor · disambiguated record
Jaskirat Bindra
Also filed as: BINDRA JASKIRAT
6 granted patents·5 citations·filing 2016–2020
73Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD6
Top patents by PatentIndex Score
6 records- 0178US10476490B2Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Nov 12, 2019·3 cites·20 claims
- 0269US10819325B2Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 27, 2020·1 cites·20 claims
- 0369US10748849B2Tapering discrete interconnection for an integrated circuit (IC)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 18, 2020·1 cites·20 claims
- 0465US11239163B2Tapering discrete interconnection for an integrated circuit (IC)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Feb 1, 2022·0 cites·20 claims
- 0565US11201610B2Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 14, 2021·0 cites·20 claims
- 0653US10276497B2Tapering discrete interconnection for an integrated circuit (IC)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 30, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →