Inventor · disambiguated record
James Wilson Bishop
Also filed as: BISHOP JAMES W · BISHOP JAMES WILSON
25 granted patents·2 pending applications·385 citations·filing 1994–2021
95Inventor score
Top patents by PatentIndex Score
27 records- 0197US8108655B2Selecting fixed-point instructions to issue on load-store unitABERNATHY CHRISTOPHER MICHAEL·Filed 2009·Granted Jan 31, 2012·148 cites·20 claims
- 0292US8103852B2Information handling system including a processor with a bifurcated issue queueBISHOP JAMES WILSON·Filed 2008·Granted Jan 24, 2012·34 cites·14 claims
- 0389US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 0487US9928128B2In-pipe error scrubbing within a processor coreIBM·Filed 2016·Granted Mar 27, 2018·6 cites·15 claims
- 0587US7254697B2Method and apparatus for dynamic modification of microprocessor instruction group at dispatchIBM·Filed 2005·Granted Aug 7, 2007·18 cites·14 claims
- 0683US7631308B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsIBM·Filed 2005·Granted Dec 8, 2009·12 cites·3 claims
- 0780US6415402B2Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chipIBM·Filed 2001·Granted Jul 2, 2002·25 cites·7 claims
- 0879US8489863B2Processor including age tracking of issue queue instructionsBISHOP JAMES WILSON·Filed 2012·Granted Jul 16, 2013·5 cites·7 claims
- 0974US8418180B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsBISHOP JAMES WILSON·Filed 2008·Granted Apr 9, 2013·6 cites·14 claims
- 1067US7478276B2Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processorIBM·Filed 2005·Granted Jan 13, 2009·4 cites·9 claims
- 1167US5539895AHierarchical computer cache systemIBM·Filed 1994·Granted Jul 23, 1996·48 cites·18 claims
- 1261US11138050B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2019·Granted Oct 5, 2021·0 cites·20 claims
- 1359US6219813B1Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chipIBM·Filed 1998·Granted Apr 17, 2001·20 cites·2 claims
- 1458US7620801B2Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessorIBM·Filed 2005·Granted Nov 17, 2009·1 cites·5 claims
- 1556US10996995B2Saving and restoring a transaction memory stateIBM·Filed 2019·Granted May 4, 2021·0 cites·20 claims
- 1655US9846614B1ECC scrubbing in a multi-slice microprocessorIBM·Filed 2016·Granted Dec 19, 2017·0 cites·20 claims
- 1754US9110708B2Region-weighted accounting of multi-threaded processor core according to dispatch stateIBM·Filed 2013·Granted Aug 18, 2015·0 cites·7 claims
- 1851US10318356B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2016·Granted Jun 11, 2019·0 cites·12 claims
- 1950US7779234B2System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessorIBM·Filed 2007·Granted Aug 17, 2010·0 cites·18 claims
- 2049US11620134B2Constrained carries on speculative countersIBM·Filed 2021·Granted Apr 4, 2023·0 cites·19 claims
- 2149US9015449B2Region-weighted accounting of multi-threaded processor core according to dispatch stateBISHOP JAMES WILSON·Filed 2011·Granted Apr 21, 2015·0 cites·21 claims
- 2249US2010257341A1Selective Execution Dependency MatrixIBM·Filed 2009·Application pending·0 cites
- 2348US5539875AError windowing for storage subsystem recoveryIBM·Filed 1994·Granted Jul 23, 1996·20 cites·4 claims
- 2447US10223196B2ECC scrubbing method in a multi-slice microprocessorIBM·Filed 2017·Granted Mar 5, 2019·0 cites·18 claims
- 2546US5809525AMulti-level computer cache system providing plural cache controllers associated with memory address ranges and having cache directoriesIBM·Filed 1996·Granted Sep 15, 1998·20 cites·20 claims
- 2644US10387154B2Thread migration using a microcode engine of a multi-slice processorIBM·Filed 2016·Granted Aug 20, 2019·0 cites·20 claims
- 2743US2006184770A1Method of implementing precise, localized hardware-error workarounds under centralized controlIBM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →