Inventor · disambiguated record
James D. Burnett
Also filed as: BURNETT JAMES D · BURNETT JAMES DAVID
60 granted patents·7 pending applications·1,201 citations·filing 1977–2015
99Inventor score
Top patents by PatentIndex Score
67 records- 0198US6861689B2One transistor DRAM cell structure and method for formingFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Mar 1, 2005·244 cites·32 claims
- 0298US6714436B1Write operation for capacitorless RAMMOTOROLA INC·Filed 2003·Granted Mar 30, 2004·211 cites·30 claims
- 0397US7238990B2Interlayer dielectric under stress for an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 3, 2007·39 cites·15 claims
- 0496US7292495B1Integrated circuit having a memory with low voltage read/write operationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 6, 2007·45 cites·22 claims
- 0595US7285832B2Multiport single transistor bit cellHOEFLER ALEXANDER B·Filed 2005·Granted Oct 23, 2007·34 cites·16 claims
- 0694US7754560B2Integrated circuit using FinFETs and having a static random access memory (SRAM)FREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 13, 2010·27 cites·4 claims
- 0794US7352631B2Methods for programming a floating body nonvolatile memoryFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Apr 1, 2008·27 cites·18 claims
- 0894US7238555B2Single transistor memory cell with reduced programming voltagesFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 3, 2007·29 cites·12 claims
- 0993US8947970B2Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltagePELLEY PERRY H·Filed 2012·Granted Feb 3, 2015·17 cites·19 claims
- 1092US7709303B2Process for forming an electronic device including a fin-type structureFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted May 4, 2010·24 cites·20 claims
- 1190US7733711B2Circuit and method for optimizing memory sense amplifier timingFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Jun 8, 2010·22 cites·20 claims
- 1290US7542369B2Integrated circuit having a memory with low voltage read/write operationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 2, 2009·20 cites·17 claims
- 1389US8766703B1Method and apparatus for sensing on-chip characteristicsYANG JIANAN·Filed 2013·Granted Jul 1, 2014·10 cites·20 claims
- 1489US7452768B2Multiple device types including an inverted-T channel transistor and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Nov 18, 2008·14 cites·6 claims
- 1588US8633515B2Transistors with immersed contactsORLOWSKI MARIUS K·Filed 2012·Granted Jan 21, 2014·8 cites·17 claims
- 1688US7800959B2Memory having self-timed bit line boost circuit and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Sep 21, 2010·23 cites·20 claims
- 1788US7414877B2Electronic device including a static-random-access memory cell and a process of forming the electronic deviceFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Aug 19, 2008·16 cites·20 claims
- 1888US7085175B2Word line driver circuit for a static random access memory and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Aug 1, 2006·47 cites·35 claims
- 1985US7968394B2Transistor with immersed contacts and methods of forming thereofFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 28, 2011·9 cites·16 claims
- 2085US7403410B2Switch device and methodFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 22, 2008·11 cites·20 claims
- 2183US7824988B2Method of forming an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Nov 2, 2010·8 cites·19 claims
- 2283US7609541B2Memory cells with lower power consumption during a write operationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 27, 2009·15 cites·18 claims
- 2382US8685800B2Single event latch-up prevention techniques for a semiconductor deviceYANG JIANAN·Filed 2012·Granted Apr 1, 2014·6 cites·15 claims
- 2482US8156357B2Voltage-based memory size scaling in a data processing systemZHANG SHAYAN·Filed 2009·Granted Apr 10, 2012·12 cites·20 claims
- 2582US7336533B2Electronic device and method for operating a memory circuitFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 26, 2008·14 cites·17 claims
- 2681US7440313B2Two-port SRAM having improved write operationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 21, 2008·13 cites·20 claims
- 2780US7483327B2Apparatus and method for adjusting an operating parameter of an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 27, 2009·12 cites·19 claims
- 2879US8531899B2Methods for testing a memory embedded in an integrated circuitZHANG SHAYAN·Filed 2012·Granted Sep 10, 2013·6 cites·11 claims
- 2979US4141322AInsecticidal collar for animalsEVANS MACK N·Filed 1977·Granted Feb 27, 1979·37 cites·3 claims
- 3078US8379466B2Integrated circuit having an embedded memory and method for testing the memoryFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Feb 19, 2013·10 cites·12 claims
- 3178US7939412B2Process for forming an electronic device including a fin-type transistor structureFREESCALE SEMICONDUCTOR INC·Filed 2010·Granted May 10, 2011·4 cites·20 claims
- 3277US7195983B2Programming, erasing, and reading structure for an NVM cellFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Mar 27, 2007·21 cites·27 claims
- 3376US7684264B2Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM arrayFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 23, 2010·10 cites·20 claims
- 3476US5541132AInsulated gate semiconductor device and method of manufactureMOTOROLA INC·Filed 1995·Granted Jul 30, 1996·46 cites·19 claims
- 3575US7517741B2Single transistor memory cell with reduced recombination ratesFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Apr 14, 2009·5 cites·21 claims
- 3673US7986006B2Single transistor memory cell with reduced recombination ratesFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Jul 26, 2011·4 cites·10 claims
- 3771US6760270B2Erase of a non-volatile memoryMOTOROLA INC·Filed 2002·Granted Jul 6, 2004·17 cites·24 claims
- 3870US9111638B2SRAM bit cell with reduced bit line pre-charge voltageBURNETT JAMES D·Filed 2012·Granted Aug 18, 2015·4 cites·18 claims
- 3970US7488635B2Semiconductor structure with reduced gate doping and methods for forming thereofFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Feb 10, 2009·3 cites·19 claims
- 4069US6327182B1Semiconductor device and a method of operation the sameMOTOROLA INC·Filed 1999·Granted Dec 4, 2001·30 cites·12 claims
- 4167US7799644B2Transistor with asymmetry for data storage circuitryFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Sep 21, 2010·3 cites·17 claims
- 4264US8659322B2Memory having a latching sense amplifier resistant to negative bias temperature instability and method thereforHOEFLER ALEXANDER B·Filed 2011·Granted Feb 25, 2014·3 cites·19 claims
- 4364US7723805B2Electronic device including a fin-type transistor structure and a process for forming the electronic deviceFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted May 25, 2010·2 cites·19 claims
- 4464US7608898B2One transistor DRAM cell structureFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 27, 2009·2 cites·15 claims
- 4563US8283244B2Method for forming one transistor DRAM cell structureBURNETT JAMES D·Filed 2009·Granted Oct 9, 2012·2 cites·18 claims
- 4659US8643066B2Multiple device types including an inverted-T channel transistor and method thereforMIN BYOUNG L·Filed 2008·Granted Feb 4, 2014·3 cites·8 claims
- 4758US7105430B2Method for forming a semiconductor device having a notched control electrode and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Sep 12, 2006·5 cites·15 claims
- 4857US6846716B2Integrated circuit device and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 25, 2005·5 cites·5 claims
- 4956US7718485B2Interlayer dielectric under stress for an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 18, 2010·1 cites·3 claims
- 5055US7269090B2Memory access with consecutive addresses corresponding to different rowsFREESCALE SEMICONDUCTOR INC·Filed 2001·Granted Sep 11, 2007·9 cites·35 claims
Showing the top 50 of 67 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →