Inventor · disambiguated record
James B. Crossland
Also filed as: CROSSLAND JAMES B
53 granted patents·8 pending applications·879 citations·filing 2001–2021
98Inventor score
Top patents by PatentIndex Score
61 records- 0197US7546487B2OS and firmware coordinated error handling using transparent firmware intercept and firmware servicesINTEL CORP·Filed 2005·Granted Jun 9, 2009·85 cites·13 claims
- 0296US7328293B2Queued locks using monitor-memory waitINTEL CORP·Filed 2007·Granted Feb 5, 2008·47 cites·21 claims
- 0395US7363474B2Method and apparatus for suspending execution of a thread until a specified memory access occursINTEL CORP·Filed 2001·Granted Apr 22, 2008·104 cites·18 claims
- 0493US7127561B2Coherency techniques for suspending execution of a thread until a specified memory access occursINTEL CORP·Filed 2001·Granted Oct 24, 2006·95 cites·36 claims
- 0592US9081707B2Apparatus and method for tracking TLB flushes on a per thread basisCONRAD SHAUN M·Filed 2012·Granted Jul 14, 2015·26 cites·21 claims
- 0692US7962771B2Method, system, and apparatus for rerouting interrupts in a multi-core processorINTEL CORP·Filed 2007·Granted Jun 14, 2011·28 cites·28 claims
- 0791US9043521B2Technique for communicating interrupts in a computer systemINTEL CORP·Filed 2012·Granted May 26, 2015·18 cites·20 claims
- 0891US7191349B2Mechanism for processor power state aware distribution of lowest priority interruptINTEL CORP·Filed 2002·Granted Mar 13, 2007·59 cites·36 claims
- 0990US7117311B1Hot plug cache coherent interface method and apparatusINTEL CORP·Filed 2001·Granted Oct 3, 2006·59 cites·26 claims
- 1089US9529708B2Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from softwarePUTHIYEDATH LEENA K·Filed 2011·Granted Dec 27, 2016·14 cites·15 claims
- 1189US7627706B2Creation of logical APIC ID with cluster ID and intra-cluster IDINTEL CORP·Filed 2007·Granted Dec 1, 2009·22 cites·22 claims
- 1288US7769938B2Processor selection for an interrupt identifying a processor clusterINTEL CORP·Filed 2007·Granted Aug 3, 2010·18 cites·22 claims
- 1386US8032681B2Processor selection for an interrupt based on willingness to accept the interrupt and on priorityINTEL CORP·Filed 2007·Granted Oct 4, 2011·15 cites·19 claims
- 1486US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 1584US8103816B2Technique for communicating interrupts in a computer systemTIRUVALLUR KESHAVAN·Filed 2008·Granted Jan 24, 2012·19 cites·21 claims
- 1684US7640384B2Queued locks using monitor-memory waitINTEL CORP·Filed 2007·Granted Dec 29, 2009·10 cites·21 claims
- 1783US9317360B2Machine check summary registerVARGAS JOSE A·Filed 2011·Granted Apr 19, 2016·11 cites·18 claims
- 1883US9158703B2Linear to physical address translation with support for page attributesINTEL CORP·Filed 2014·Granted Oct 13, 2015·4 cites·13 claims
- 1983US7822900B2Apparatus and method for enumeration of processors during hot-plug of a compute nodeINTEL CORP·Filed 2008·Granted Oct 26, 2010·10 cites·20 claims
- 2081US8230203B2Detecting spin loops in a virtual machine environmentNEIGER GILBERT·Filed 2007·Granted Jul 24, 2012·11 cites·10 claims
- 2180US7565492B2Method and apparatus for preventing software side channel attacksINTEL CORP·Filed 2006·Granted Jul 21, 2009·9 cites·21 claims
- 2280US7213093B2Queued locks using monitor-memory waitINTEL CORP·Filed 2003·Granted May 1, 2007·22 cites·14 claims
- 2380US6920581B2Method and apparatus for functional redundancy check mode recoveryINTEL CORP·Filed 2002·Granted Jul 19, 2005·29 cites·24 claims
- 2479US9916257B2Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memorySANKARAN RAJESH M·Filed 2011·Granted Mar 13, 2018·6 cites·20 claims
- 2579US8635415B2Managing and implementing metadata in central processing unit using register extensionsPATEL BAIJU V·Filed 2009·Granted Jan 21, 2014·11 cites·13 claims
- 2679US7673090B2Hot plug interface control method and apparatusINTEL CORP·Filed 2001·Granted Mar 2, 2010·28 cites·27 claims
- 2778US9239801B2Systems and methods for preventing unauthorized stack pivotingINTEL CORP·Filed 2013·Granted Jan 19, 2016·5 cites·19 claims
- 2878US8312198B2Technique for communicating interrupts in a computer systemTIRUVALLUR KESHAVAN·Filed 2012·Granted Nov 13, 2012·5 cites·24 claims
- 2977US7761720B2Mechanism for processor power state aware distribution of lowest priority interruptsINTEL CORP·Filed 2007·Granted Jul 20, 2010·7 cites·22 claims
- 3076US9164917B2Linear to physical address translation with support for page attributesINTEL CORP·Filed 2014·Granted Oct 20, 2015·2 cites·13 claims
- 3176US9164916B2Linear to physical address translation with support for page attributesINTEL CORP·Filed 2014·Granted Oct 20, 2015·2 cites·13 claims
- 3274US6917999B2Platform and method for initializing components within hot-plugged nodesINTEL CORP·Filed 2001·Granted Jul 12, 2005·20 cites·25 claims
- 3373US7493438B2Apparatus and method for enumeration of processors during hot-plug of a compute nodeINTEL CORP·Filed 2001·Granted Feb 17, 2009·15 cites·29 claims
- 3472US9524227B2Apparatuses and methods for generating a suppressed address traceINTEL CORP·Filed 2014·Granted Dec 20, 2016·2 cites·25 claims
- 3572US7000102B2Platform and method for supporting hibernate operationsINTEL CORP·Filed 2001·Granted Feb 14, 2006·17 cites·17 claims
- 3671US10001953B2System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storageINTEL CORP·Filed 2016·Granted Jun 19, 2018·1 cites·18 claims
- 3771US9852069B2RAM disk using non-volatile random access memoryINTEL CORP·Filed 2016·Granted Dec 26, 2017·1 cites·16 claims
- 3869US9207940B2Robust and high performance instructions for system callPATEL BAIJU V·Filed 2013·Granted Dec 8, 2015·2 cites·20 claims
- 3967US8799620B2Linear to physical address translation with support for page attributesFALIK OHAD·Filed 2007·Granted Aug 5, 2014·2 cites·26 claims
- 4064US12020031B2Methods, apparatus, and instructions for user-level thread suspensionINTEL CORP·Filed 2021·Granted Jun 25, 2024·0 cites·18 claims
- 4164US8631261B2Context state management for processor feature setsVAN DYKE DON A·Filed 2007·Granted Jan 14, 2014·4 cites·17 claims
- 4262US11074191B2Linear to physical address translation with support for page attributesINTEL CORP·Filed 2017·Granted Jul 27, 2021·0 cites·28 claims
- 4362US8677163B2Context state management for processor feature setsVAN DYKE DON·Filed 2013·Granted Mar 18, 2014·2 cites·11 claims
- 4457US2016041921A1Linear to physical address translation with support for page attributesINTEL CORP·Filed 2015·Application pending·0 cites
- 4556US9535827B2RAM disk using non-volatile random access memoryCROSSLAND JAMES B·Filed 2011·Granted Jan 3, 2017·2 cites·19 claims
- 4655US7581042B2I/O hub resident cache line monitor and device register updateINTEL CORP·Filed 2004·Granted Aug 25, 2009·4 cites·29 claims
- 4754US8122230B2Using a processor identification instruction to provide multi-level processor topology informationPUTHIYEDATH LEENA K·Filed 2007·Granted Feb 21, 2012·1 cites·20 claims
- 4853US10346167B2Apparatuses and methods for generating a suppressed address traceINTEL CORP·Filed 2016·Granted Jul 9, 2019·0 cites·25 claims
- 4952US11023233B2Methods, apparatus, and instructions for user level thread suspensionINTEL CORP·Filed 2016·Granted Jun 1, 2021·0 cites·15 claims
- 5052US8984199B2Inter-processor interruptsHAMMARLUND PER·Filed 2003·Granted Mar 17, 2015·5 cites·15 claims
Showing the top 50 of 61 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →