Inventor · disambiguated record
James Stephen Fields, Jr.
Also filed as: FIELDS JAMES · FIELDS JAMES S · FIELDS JAMES S JR · FIELDS JAMES STEPHEN
144 granted patents·14 pending applications·3,174 citations·filing 1993–2025
99Inventor score
Top patents by PatentIndex Score
158 records- 0196US7421598B2Dynamic power management via DIMM read operation limiterIBM·Filed 2005·Granted Sep 2, 2008·69 cites·6 claims
- 0296US7194645B2Method and apparatus for autonomic policy-based thermal management in a data processing systemIBM·Filed 2005·Granted Mar 20, 2007·63 cites·20 claims
- 0395US7305522B2Victim cache using direct interventionIBM·Filed 2005·Granted Dec 4, 2007·40 cites·1 claims
- 0494US7584329B2Data processing system and method for efficient communication utilizing an Ig coherency stateIBM·Filed 2005·Granted Sep 1, 2009·36 cites·21 claims
- 0594US7467323B2Data processing system and method for efficient storage of metadata in a system memoryIBM·Filed 2005·Granted Dec 16, 2008·33 cites·10 claims
- 0693US7389388B2Data processing system and method for efficient communication utilizing an in coherency stateIBM·Filed 2005·Granted Jun 17, 2008·29 cites·8 claims
- 0792US7827354B2Victim cache using direct interventionIBM·Filed 2007·Granted Nov 2, 2010·23 cites·9 claims
- 0891US6754782B2Decentralized global coherency management in a multi-node computer systemIBM·Filed 2001·Granted Jun 22, 2004·71 cites·24 claims
- 0991US6615322B2Two-stage request protocol for accessing remote memory data in a NUMA data processing systemIBM·Filed 2001·Granted Sep 2, 2003·70 cites·15 claims
- 1089US12219691B2Printed circuit board assembly with integrated vapor chamberNVIDIA CORP·Filed 2022·Granted Feb 4, 2025·2 cites·17 claims
- 1189US6704843B1Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchangeIBM·Filed 2000·Granted Mar 9, 2004·59 cites·21 claims
- 1289US6405289B1Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop responseIBM·Filed 1999·Granted Jun 11, 2002·148 cites·14 claims
- 1388US6760817B2Method and system for prefetching utilizing memory initiated prefetch write operationsIBM·Filed 2001·Granted Jul 6, 2004·52 cites·22 claims
- 1488US6711652B2Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified dataIBM·Filed 2001·Granted Mar 23, 2004·53 cites·17 claims
- 1588US6658538B2Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency controlIBM·Filed 2001·Granted Dec 2, 2003·52 cites·14 claims
- 1688US6601144B1Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysisIBM·Filed 2000·Granted Jul 29, 2003·53 cites·36 claims
- 1787US6901485B2Memory directory management in a multi-node computer systemIBM·Filed 2001·Granted May 31, 2005·46 cites·23 claims
- 1887US6633959B2Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared dataIBM·Filed 2001·Granted Oct 14, 2003·50 cites·11 claims
- 1986US7454577B2Data processing system and method for efficient communication utilizing an Tn and Ten coherency statesIBM·Filed 2005·Granted Nov 18, 2008·14 cites·14 claims
- 2085US7484131B2System and method for recovering from a hang condition in a data processing systemIBM·Filed 2005·Granted Jan 27, 2009·12 cites·6 claims
- 2185US7467204B2Method for providing low-level hardware access to in-band and out-of-band firmwareIBM·Filed 2005·Granted Dec 16, 2008·14 cites·1 claims
- 2285US6629210B1Intelligent cache management mechanism via processor access sequence analysisIBM·Filed 2000·Granted Sep 30, 2003·42 cites·16 claims
- 2384US7007210B2Method and system for handling multiple bit errors to enhance system reliabilityIBM·Filed 2002·Granted Feb 28, 2006·38 cites·80 claims
- 2483US7454578B2Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memoryIBM·Filed 2005·Granted Nov 18, 2008·12 cites·20 claims
- 2583US6763433B1High performance cache intervention mechanism for symmetric multiprocessor systemsIBM·Filed 2000·Granted Jul 13, 2004·36 cites·19 claims
- 2682US10207462B1Printer assemblyFIELDS JAMES·Filed 2015·Granted Feb 19, 2019·10 cites·14 claims
- 2782US8139592B2Ticket-based operation trackingCLARK LEO J·Filed 2008·Granted Mar 20, 2012·11 cites·15 claims
- 2882US7734876B2Protecting ownership transfer with non-uniform protection windowsIBM·Filed 2006·Granted Jun 8, 2010·11 cites·14 claims
- 2982US6721856B1Enhanced cache management mechanism via an intelligent system bus monitorIBM·Filed 2000·Granted Apr 13, 2004·33 cites·18 claims
- 3082US6393528B1Optimized cache allocation algorithm for multiple speculative requestsIBM·Filed 1999·Granted May 21, 2002·97 cites·21 claims
- 3181US7308537B2Half-good mode for large L2 cache array topology with different latency domainsIBM·Filed 2005·Granted Dec 11, 2007·11 cites·15 claims
- 3281US6434669B1Method of cache management to dynamically update information-type dependent cache policiesIBM·Filed 1999·Granted Aug 13, 2002·95 cites·23 claims
- 3381US6356980B1Method and system for bypassing cache levels when casting out from an upper level cacheIBM·Filed 1999·Granted Mar 12, 2002·90 cites·20 claims
- 3481US6275907B1Reservation management in a non-uniform memory access (NUMA) data processing systemIBM·Filed 1998·Granted Aug 14, 2001·97 cites·19 claims
- 3580US7116142B2Apparatus and method for accurately tuning the speed of an integrated circuitIBM·Filed 2004·Granted Oct 3, 2006·22 cites·20 claims
- 3680US6848003B1Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined responseIBM·Filed 1999·Granted Jan 25, 2005·87 cites·20 claims
- 3780US6591321B1Multiprocessor system bus protocol with group addresses, responses, and prioritiesIBM·Filed 1999·Granted Jul 8, 2003·89 cites·24 claims
- 3879US7143226B2Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip linkIBM·Filed 2005·Granted Nov 28, 2006·9 cites·20 claims
- 3979US6470427B1Programmable agent and method for managing prefetch queuesIBM·Filed 1999·Granted Oct 22, 2002·82 cites·20 claims
- 4078US7779292B2Efficient storage of metadata in a system memoryIBM·Filed 2007·Granted Aug 17, 2010·7 cites·5 claims
- 4178US7483422B2Data processing system, method and interconnect fabric for selective link information allocation in a data processing systemIBM·Filed 2005·Granted Jan 27, 2009·7 cites·6 claims
- 4277US6760809B2Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memoryIBM·Filed 2001·Granted Jul 6, 2004·23 cites·15 claims
- 4377US6473833B1Integrated cache and directory structure for multi-level cachesIBM·Filed 1999·Granted Oct 29, 2002·76 cites·8 claims
- 4477US6408362B1Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached dataIBM·Filed 1999·Granted Jun 18, 2002·76 cites·21 claims
- 4577US2025275082A1Cable cartridges and associated connection methods for disaggregated server architecturesNVIDIA CORP·Filed 2025·Application pending·0 cites
- 4677US2025275103A1Datacenter rack with disaggregated server architecturesNVIDIA CORP·Filed 2025·Application pending·0 cites
- 4777US2025275079A1Disaggregated server architectureNVIDIA CORP·Filed 2025·Application pending·0 cites
- 4877US2025275081A1Network topology for disaggregated server architecturesNVIDIA CORP·Filed 2025·Application pending·0 cites
- 4976US8140770B2Data processing system and method for predictively selecting a scope of broadcast of an operationCLARK LEO J·Filed 2005·Granted Mar 20, 2012·8 cites·20 claims
- 5076US7243194B2Method to preserve ordering of read and write operations in a DMA system by delaying read accessIBM·Filed 2005·Granted Jul 10, 2007·8 cites·20 claims
Showing the top 50 of 158 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →