Inventor · disambiguated record
Jay Fleischman
Also filed as: FLEISCHMAN JAY · FLEISCHMAN JAY E
30 granted patents·9 pending applications·484 citations·filing 1998–2023
96Inventor score
Files withADVANCED MICRO DEVICES INC20HEWLETT PACKARD CO7FLEISCHMAN JAY5FLEISCHMAN JAY E3ESTLICK MICHAEL D2
Top patents by PatentIndex Score
39 records- 0198US11868777B2Processor-guided execution of offloaded instructions using fixed function operationsADVANCED MICRO DEVICES INC·Filed 2020·Granted Jan 9, 2024·12 cites·20 claims
- 0295US12153926B2Processor-guided execution of offloaded instructions using fixed function operationsADVANCED MICRO DEVICES INC·Filed 2023·Granted Nov 26, 2024·3 cites·20 claims
- 0393US6550023B1On-the-fly memory testing and automatic generation of bitmapsHEWLETT PACKARD DEVELOPMENT CO·Filed 1998·Granted Apr 15, 2003·119 cites·23 claims
- 0488US6374370B1Method and system for flexible control of BIST registers based upon on-chip eventsHEWLETT PACKARD CO·Filed 1998·Granted Apr 16, 2002·158 cites·35 claims
- 0586US6321320B1Flexible and programmable BIST engine for on-chip memory array testing and characterizationHEWLETT PACKARD CO·Filed 1998·Granted Nov 20, 2001·71 cites·92 claims
- 0686US6249465B1Redundancy programming using addressable scan paths to reduce the number of required fusesHEWLETT PACKARD CO·Filed 2000·Granted Jun 19, 2001·45 cites·20 claims
- 0777US10700954B2Scheduling memory bandwidth based on quality of service floorbackgroundADVANCED MICRO DEVICES INC·Filed 2017·Granted Jun 30, 2020·2 cites·19 claims
- 0875US11163688B2System probe aware last level cache insertion bypassingADVANCED MICRO DEVICES INC·Filed 2019·Granted Nov 2, 2021·1 cites·20 claims
- 0974US6141779AMethod for automatically programming a redundancy map for a redundant circuitHEWLETT PACKARD CO·Filed 1998·Granted Oct 31, 2000·35 cites·17 claims
- 1073US12333309B2Differential pipeline delays in a coprocessorADVANCED MICRO DEVICES INC·Filed 2023·Granted Jun 17, 2025·0 cites·20 claims
- 1173US6298429B1Memory address generator capable of row-major and column-major sweepsHEWLETT PACKARD CO·Filed 2000·Granted Oct 2, 2001·20 cites·13 claims
- 1269US12204454B2System probe aware last level cache insertion bypassingADVANCED MICRO DEVICES INC·Filed 2021·Granted Jan 21, 2025·0 cites·20 claims
- 1366US8868633B2Method and circuitry for square root determinationLEMONDS CARL E·Filed 2012·Granted Oct 21, 2014·3 cites·21 claims
- 1463US9575763B2Accelerated reversal of speculative state changes and resource recoveryADVANCED MICRO DEVICES INC·Filed 2013·Granted Feb 21, 2017·1 cites·20 claims
- 1561US12299445B2Register based SIMD lookup table operationsADVANCED MICRO DEVICES INC·Filed 2022·Granted May 13, 2025·0 cites·20 claims
- 1661US11847062B2Re-fetching data for L3 cache data evictions into a last-level cacheADVANCED MICRO DEVICES INC·Filed 2021·Granted Dec 19, 2023·0 cites·20 claims
- 1760US12282428B2Selective speculative prefetch requests for a last-level cacheADVANCED MICRO DEVICES INC·Filed 2021·Granted Apr 22, 2025·0 cites·20 claims
- 1858US8769247B2Processor with increased efficiency via early instruction completionESTLICK MICHAEL D·Filed 2011·Granted Jul 1, 2014·1 cites·15 claims
- 1955US11709681B2Differential pipeline delays in a coprocessorADVANCED MICRO DEVICES INC·Filed 2017·Granted Jul 25, 2023·0 cites·20 claims
- 2052US2024095180A1Systems and methods for interpolating register-based lookup tablesADVANCED MICRO DEVICES INC·Filed 2022·Application pending·0 cites
- 2152US2024319964A1Large number integer addition using vector accumulationADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 2250US9959122B2Single cycle instruction pipeline schedulingADVANCED MICRO DEVICES INC·Filed 2013·Granted May 1, 2018·0 cites·20 claims
- 2349US11550728B2System and method for page table caching memoryADVANCED MICRO DEVICES INC·Filed 2019·Granted Jan 10, 2023·0 cites·20 claims
- 2448US11023241B2Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelinesADVANCED MICRO DEVICES INC·Filed 2018·Granted Jun 1, 2021·0 cites·25 claims
- 2547US9910638B1Computer-based square root and division operationsADVANCED MICRO DEVICES INC·Filed 2016·Granted Mar 6, 2018·0 cites·20 claims
- 2646US8671288B2Processor with power control via instruction issuanceFLEISCHMAN JAY·Filed 2010·Granted Mar 11, 2014·0 cites·16 claims
- 2746US2015121040A1Processor and methods for floating point register aliasingADVANCED MICRO DEVICES INC·Filed 2014·Application pending·0 cites
- 2845US11567554B2Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristicsADVANCED MICRO DEVICES INC·Filed 2017·Granted Jan 31, 2023·0 cites·20 claims
- 2945US10223162B2Mechanism for resource utilization metering in a computer systemADVANCED MICRO DEVICES INC·Filed 2016·Granted Mar 5, 2019·0 cites·17 claims
- 3039US8819397B2Processor with increased efficiency via control word predictionESTLICK MICHAEL D·Filed 2011·Granted Aug 26, 2014·0 cites·15 claims
- 3138US2012191956A1Processor having increased performance and energy saving via operand remappingFLEISCHMAN JAY·Filed 2011·Application pending·0 cites
- 3237US6233669B1Memory address generator capable of row-major and column-major sweepsHEWLETT PACKARD CO·Filed 1998·Granted May 15, 2001·6 cites·20 claims
- 3337US2012173854A1Processor having increased effective physical file size via register mappingFLEISCHMAN JAY·Filed 2010·Application pending·0 cites
- 3437US2012191954A1Processor having increased performance and energy saving via instruction pre-completionFLEISCHMAN JAY·Filed 2011·Application pending·0 cites
- 3537US2012005459A1Processor having increased performance and energy saving via move eliminationFLEISCHMAN JAY·Filed 2010·Application pending·0 cites
- 3636US6175518B1Remote register hierarchy accessible using a serial data lineHEWLETT PACKARD CO·Filed 1999·Granted Jan 16, 2001·7 cites·23 claims
- 3735US9268575B2Flush operations in a processorFLEISCHMAN JAY E·Filed 2011·Granted Feb 23, 2016·0 cites·18 claims
- 3833US2012166769A1Processor having increased performance via elimination of serial dependenciesFLEISCHMAN JAY E·Filed 2010·Application pending·0 cites
- 3932US2012191952A1Processor implementing scalar code optimizationFLEISCHMAN JAY E·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Jay Fleischman files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →