Inventor · disambiguated record
Jack T. Kavalieros
Also filed as: KAVALIEROS JACK · KAVALIEROS JACK T · TOLCHINSKY PETER
627 granted patents·167 pending applications·9,327 citations·filing 1998–2025
99Inventor score
Top patents by PatentIndex Score
794 records- 0199US8987794B2Non-planar gate all-around device and method of fabrication thereofRACHMADY WILLY·Filed 2011·Granted Mar 24, 2015·65 cites·29 claims
- 0299US7825437B2Unity beta ratio tri-gate transistor static random access memory (SRAM)INTEL CORP·Filed 2007·Granted Nov 2, 2010·166 cites·17 claims
- 0399US7531437B2Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric materialINTEL CORP·Filed 2006·Granted May 12, 2009·195 cites·10 claims
- 0499US7518196B2Field effect transistor with narrow bandgap source and drain regions and method of fabricationINTEL CORP·Filed 2005·Granted Apr 14, 2009·72 cites·22 claims
- 0599US7485536B2Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriersINTEL CORP·Filed 2005·Granted Feb 3, 2009·155 cites·4 claims
- 0699US6858478B2Tri-gate devices and methods of fabricationINTEL CORP·Filed 2003·Granted Feb 22, 2005·629 cites·3 claims
- 0798US11923410B2Transistor with isolation below source and drainINTEL CORP·Filed 2021·Granted Mar 5, 2024·4 cites·23 claims
- 0898US9123567B2CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architectureRADOSAVLJEVIC MARKO·Filed 2011·Granted Sep 1, 2015·66 cites·26 claims
- 0998US8847281B2High mobility strained channels for fin-based transistorsCEA STEPHEN M·Filed 2012·Granted Sep 30, 2014·47 cites·22 claims
- 1098US8294180B2CMOS devices with a single work function gate electrode and method of fabricationDOYLE BRIAN S·Filed 2011·Granted Oct 23, 2012·37 cites·14 claims
- 1198US8283653B2Non-planar germanium quantum well devicesPILLARISETTY RAVI·Filed 2009·Granted Oct 9, 2012·47 cites·20 claims
- 1298US8110877B2Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regionsMUKHERJEE NILOY·Filed 2008·Granted Feb 7, 2012·108 cites·15 claims
- 1398US7898041B2Block contact architectures for nanoscale channel transistorsINTEL CORP·Filed 2007·Granted Mar 1, 2011·113 cites·20 claims
- 1498US7893506B2Field effect transistor with narrow bandgap source and drain regions and method of fabricationINTEL CORP·Filed 2010·Granted Feb 22, 2011·35 cites·10 claims
- 1598US7745270B2Tri-gate patterning using dual layer gate stackINTEL CORP·Filed 2007·Granted Jun 29, 2010·121 cites·20 claims
- 1698US7569443B2Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gateINTEL CORP·Filed 2005·Granted Aug 4, 2009·72 cites·9 claims
- 1798US7569857B2Dual crystal orientation circuit devices on the same substrateINTEL CORP·Filed 2006·Granted Aug 4, 2009·119 cites·4 claims
- 1898US7547637B2Methods for patterning a semiconductor filmINTEL CORP·Filed 2005·Granted Jun 16, 2009·52 cites·8 claims
- 1998US7485503B2Dielectric interface for group III-V semiconductor deviceINTEL CORP·Filed 2005·Granted Feb 3, 2009·63 cites·13 claims
- 2098US7479421B2Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made therebyINTEL CORP·Filed 2005·Granted Jan 20, 2009·105 cites·2 claims
- 2198US7449373B2Method of ion implanting for tri-gate devicesINTEL CORP·Filed 2006·Granted Nov 11, 2008·74 cites·19 claims
- 2298US7358121B2Tri-gate devices and methods of fabricationINTEL CORP·Filed 2002·Granted Apr 15, 2008·153 cites·15 claims
- 2398US7279375B2Block contact architectures for nanoscale channel transistorsINTEL CORP·Filed 2005·Granted Oct 9, 2007·93 cites·12 claims
- 2498US7170120B2Carbon nanotube energy well (CNEW) field effect transistorINTEL CORP·Filed 2005·Granted Jan 30, 2007·149 cites·15 claims
- 2598US6696345B2Metal-gate electrode for CMOS transistor applicationsINTEL CORP·Filed 2002·Granted Feb 24, 2004·164 cites·13 claims
- 2697US11063131B2Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineeringINTEL CORP·Filed 2019·Granted Jul 13, 2021·31 cites·11 claims
- 2797US9252275B2Non-planar gate all-around device and method of fabrication thereofINTEL CORP·Filed 2014·Granted Feb 2, 2016·20 cites·19 claims
- 2897US9240410B2Group III-N nanowire transistorsTHEN HAN WUI·Filed 2011·Granted Jan 19, 2016·25 cites·17 claims
- 2997US8952541B2Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processesMUKHERJEE NILOY·Filed 2012·Granted Feb 10, 2015·36 cites·5 claims
- 3097US8901537B2Transistors with high concentration of boron doped germaniumMURTHY ANAND S·Filed 2010·Granted Dec 2, 2014·56 cites·25 claims
- 3197US8765563B2Trench confined epitaxially grown device layer(s)PILLARISETTY RAVI·Filed 2012·Granted Jul 1, 2014·42 cites·9 claims
- 3297US8575596B2Non-planar germanium quantum well devicesPILLARISETTY RAVI·Filed 2012·Granted Nov 5, 2013·24 cites·14 claims
- 3397US8211772B2Two-dimensional condensation for uniaxially strained semiconductor finsKAVALIEROS JACK T·Filed 2009·Granted Jul 3, 2012·72 cites·20 claims
- 3497US8110458B2Fabrication of germanium nanowire transistorsJIN BEEN-YIH·Filed 2010·Granted Feb 7, 2012·51 cites·15 claims
- 3597US7838373B2Replacement spacers for MOSFET fringe capacitance reduction and processes of making sameINTEL CORP·Filed 2008·Granted Nov 23, 2010·52 cites·21 claims
- 3697US7821061B2Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applicationsINTEL CORP·Filed 2007·Granted Oct 26, 2010·41 cites·5 claims
- 3797US7525160B2Multigate device with recessed strain regionsINTEL CORP·Filed 2005·Granted Apr 28, 2009·65 cites·14 claims
- 3897US7494862B2Methods for uniform doping of non-planar transistor structuresINTEL CORP·Filed 2006·Granted Feb 24, 2009·70 cites·10 claims
- 3997US7456068B2Forming ultra-shallow junctionsINTEL CORP·Filed 2006·Granted Nov 25, 2008·66 cites·15 claims
- 4097US7355281B2Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrodeINTEL CORP·Filed 2006·Granted Apr 8, 2008·47 cites·12 claims
- 4197US7316949B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2005·Granted Jan 8, 2008·50 cites·13 claims
- 4297US7208361B2Replacement gate process for making a semiconductor device that includes a metal gate electrodeINTEL CORP·Filed 2004·Granted Apr 24, 2007·128 cites·20 claims
- 4397US7126199B2Multilayer metal gate electrodeINTEL CORP·Filed 2004·Granted Oct 24, 2006·154 cites·5 claims
- 4497US7005366B2Tri-gate devices and methods of fabricationINTEL CORP·Filed 2004·Granted Feb 28, 2006·121 cites·5 claims
- 4597US6653700B2Transistor structure and method of fabricationINTEL CORP·Filed 2002·Granted Nov 25, 2003·144 cites·8 claims
- 4696US11996411B2Stacked forksheet transistorsINTEL CORP·Filed 2020·Granted May 28, 2024·4 cites·21 claims
- 4796US11862730B2Top-gate doped thin film transistorINTEL CORP·Filed 2022·Granted Jan 2, 2024·2 cites·20 claims
- 4896US11843058B2Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structuresINTEL CORP·Filed 2021·Granted Dec 12, 2023·3 cites·18 claims
- 4996US10038054B2Variable gate width for gate all-around transistorsINTEL CORP·Filed 2017·Granted Jul 31, 2018·14 cites·15 claims
- 5096US9627384B2Transistors with high concentration of boron doped germaniumINTEL CORP·Filed 2014·Granted Apr 18, 2017·12 cites·20 claims
Showing the top 50 of 794 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →