Inventor · disambiguated record
James W. Keeley
Also filed as: KEELEY JAMES W
35 granted patents·1,303 citations·filing 1982–2009
98Inventor score
Files withBULL HN INFORMATION SYST19HONEYWELL INF SYSTEMS7HONEYWELL BULL6BULL HN INFORAMTION SYSTEMS IN1KEELEY JAMES W1
Top patents by PatentIndex Score
35 records- 0195US4575792AShared interface apparatus for testing the memory sections of a cache unitHONEYWELL INF SYSTEMS·Filed 1982·Granted Mar 11, 1986·82 cites·31 claims
- 0292US4695943AMultiprocessor shared pipeline cache memory with split cycle and concurrent utilizationHONEYWELL INF SYSTEMS·Filed 1984·Granted Sep 22, 1987·113 cites·33 claims
- 0391US4763243AResilient bus systemHONEYWELL BULL·Filed 1984·Granted Aug 9, 1988·90 cites·20 claims
- 0489US4764862AResilient bus systemHONEYWELL BULL·Filed 1985·Granted Aug 16, 1988·96 cites·24 claims
- 0587US5274797AMultiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timingBULL HN INFORMATION SYST·Filed 1989·Granted Dec 28, 1993·57 cites·21 claims
- 0683US5193181ARecovery method and apparatus for a pipelined processing unit of a multiprocessor systemBULL HN INFORMATION SYST·Filed 1990·Granted Mar 9, 1993·102 cites·18 claims
- 0783US4785395AMultiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacementHONEYWELL BULL·Filed 1986·Granted Nov 15, 1988·80 cites·25 claims
- 0882US4464717AMultilevel cache system with graceful degradation capabilityHONEYWELL INF SYSTEMS·Filed 1982·Granted Aug 7, 1984·64 cites·36 claims
- 0980US4833601ACache resiliency in processing a variety of address faultsBULL HN INFORMATION SYST·Filed 1987·Granted May 23, 1989·65 cites·21 claims
- 1076US4667288AEnable/disable control checking apparatusHONEYWELL INF SYSTEMS·Filed 1983·Granted May 19, 1987·47 cites·28 claims
- 1175US4686621ATest apparatus for testing a multilevel cache system with graceful degradation capabilityHONEYWELL INF SYSTEMS·Filed 1983·Granted Aug 11, 1987·44 cites·29 claims
- 1274US4768148ARead in process memory apparatusHONEYWELL BULL·Filed 1986·Granted Aug 30, 1988·50 cites·29 claims
- 1366US5367697AMeans for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capabilityBULL HN INFORMATION SYST·Filed 1991·Granted Nov 22, 1994·46 cites·3 claims
- 1466US4562536ADirectory test error mode control apparatusHONEYWELL INF SYSTEMS·Filed 1983·Granted Dec 31, 1985·31 cites·32 claims
- 1562US5283870AMethod and apparatus for avoiding processor deadly embrace in a multiprocessor systemBULL HN INFORMATION SYST·Filed 1991·Granted Feb 1, 1994·40 cites·10 claims
- 1659US4839800AData processing system with a fast interruptBULL HN INFORMATION SYST·Filed 1986·Granted Jun 13, 1989·26 cites·12 claims
- 1757US5664200AApparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor systemBULL HN INFORMATION SYST·Filed 1995·Granted Sep 2, 1997·30 cites·15 claims
- 1856US4910666AApparatus for loading and verifying a control store memory of a central subsystemBULL HN INFORMATION SYST·Filed 1986·Granted Mar 20, 1990·23 cites·5 claims
- 1954US5487163AFast synchronization of asynchronous signals with a synchronous systemBULL HN INFORMATION SYST·Filed 1993·Granted Jan 23, 1996·12 cites·12 claims
- 2052US8116330B2Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loopKEELEY JAMES W·Filed 2009·Granted Feb 14, 2012·1 cites·17 claims
- 2152US5341495ABus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocolsBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·25 cites·15 claims
- 2249US4799222AAddress transform method and apparatus for transferring addressesHONEYWELL BULL·Filed 1987·Granted Jan 17, 1989·16 cites·20 claims
- 2347US5548713AOn-board diagnostic testingBULL HN INFORMATION SYST·Filed 1994·Granted Aug 20, 1996·21 cites·12 claims
- 2447US5471638ABus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requestsBULL HN INFORAMTION SYSTEMS IN·Filed 1994·Granted Nov 28, 1995·22 cites·13 claims
- 2546US8379665B2Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop systemLSI CORP·Filed 2009·Granted Feb 19, 2013·0 cites·18 claims
- 2645US5404535AApparatus and method for providing more effective reiterations of processing task requests in a multiprocessor systemBULL HN INFORMATION SYST·Filed 1991·Granted Apr 4, 1995·14 cites·5 claims
- 2745US5210757AMethod and apparatus for performing health tests of units of a data processing systemBULL HN INFORMATION SYST·Filed 1990·Granted May 11, 1993·17 cites·18 claims
- 2844US5491790APower-on sequencing apparatus for initializing and testing a system processing unitBULL HN INFORMATION SYST·Filed 1994·Granted Feb 13, 1996·16 cites·12 claims
- 2943US5293384AMicroprocessor bus interface protocol analyzerBULL HN INFORMATION SYST·Filed 1991·Granted Mar 8, 1994·14 cites·12 claims
- 3042US5341501AProcessor bus accessBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·13 cites·11 claims
- 3142US4724519AChannel number priority assignment apparatusHONEYWELL INF SYSTEMS·Filed 1985·Granted Feb 9, 1988·12 cites·23 claims
- 3240US5446847AProgrammable system bus priority networkBULL HN INFORMATION SYST·Filed 1993·Granted Aug 29, 1995·11 cites·11 claims
- 3340US5379378AData processing system having a bus command generated by one subsystem on behalf of another subsystemBULL HN INFORMATION SYST·Filed 1991·Granted Jan 3, 1995·13 cites·10 claims
- 3435US5341508AProcessing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous busBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·7 cites·14 claims
- 3532US4802087AMultiprocessor level change synchronization apparatusHONEYWELL BULL·Filed 1986·Granted Jan 31, 1989·3 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →