Inventor · disambiguated record
Jason M. Kulick
Also filed as: KULICK JASON · KULICK JASON M
17 granted patents·5 pending applications·36 citations·filing 2012–2022
89Inventor score
Files withINDIANA INTEGRATED CIRCUITS LLC16LMX MEDTECH LLC3BIOMEMS ANALYTICS LLC1LAVEIGNE JOSEPH DONALD1UNIV NOTRE DAME DU LAC1
Top patents by PatentIndex Score
22 records- 0191US9620473B1Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignmentINDIANA INTEGRATED CIRCUITS LLC·Filed 2014·Granted Apr 11, 2017·18 cites·9 claims
- 0289US10409004B2Method and system to passively align and attach fiber array to laser array or optical waveguide arrayINDIANA INTEGRATED CIRCUITS LLC·Filed 2017·Granted Sep 10, 2019·8 cites·15 claims
- 0387US10598861B2Method and system to passively align and attach fiber array to laser array or optical waveguide arrayINDIANA INTEGRATED CIRCUITS LLC·Filed 2019·Granted Mar 24, 2020·5 cites·4 claims
- 0483US10410989B2Inter-chip alignmentUNIV NOTRE DAME DU LAC·Filed 2017·Granted Sep 10, 2019·3 cites·6 claims
- 0570US11523511B2Assembling and handling edge interconnect packaging systemINDIANA INTEGRATED CIRCUITS LLC·Filed 2021·Granted Dec 6, 2022·0 cites·3 claims
- 0667US9806030B2Prototyping of electronic circuits with edge interconnectsINDIANA INTEGRATED CIRCUITS LLC·Filed 2016·Granted Oct 31, 2017·1 cites·13 claims
- 0760US11398463B2Edge interconnect self-assembly substrateINDIANA INTEGRATED CIRCUITS LLC·Filed 2020·Granted Jul 26, 2022·0 cites·3 claims
- 0857US10945335B2Assembling and handling edge interconnect packaging systemINDIANA INTEGRATED CIRCUITS LLC·Filed 2017·Granted Mar 9, 2021·0 cites·2 claims
- 0956US2023384290A1Cellular Response Analysis MethodBIOMEMS ANALYTICS LLC·Filed 2021·Application pending·0 cites
- 1056US2023384323A1Method for Correction for Sample VolumeLMX MEDTECH LLC·Filed 2021·Application pending·0 cites
- 1156US2023384314A1Oxidative Mass LabelingLMX MEDTECH LLC·Filed 2021·Application pending·0 cites
- 1256US2023408509A1Automatic Diagnostic TracingLMX MEDTECH LLC·Filed 2021·Application pending·0 cites
- 1353US10056335B2Prototyping of electronic circuits with edge interconnectsINDIANA INTEGRATED CIRCUITS LLC·Filed 2017·Granted Aug 21, 2018·0 cites·7 claims
- 1453US9844139B2Method of interconnecting microchipsINDIANA INTEGRATED CIRCUITS LLC·Filed 2014·Granted Dec 12, 2017·0 cites·5 claims
- 1551US9163995B2Techniques for tiling arrays of pixel elementsLAVEIGNE JOSEPH DONALD·Filed 2012·Granted Oct 20, 2015·1 cites·20 claims
- 1648US10896898B2Edge interconnect self-assembly substrateINDIANA INTEGRATED CIRCUITS LLC·Filed 2016·Granted Jan 19, 2021·0 cites·13 claims
- 1748US10050027B2Quilt packaging system with mated metal interconnect nodules and voidsINDIANA INTEGRATED CIRCUITS LLC·Filed 2017·Granted Aug 14, 2018·0 cites·8 claims
- 1845US2022322532A1Three-Dimensional Printed Circuit Substrate AssemblyINDIANA INTEGRATED CIRCUITS LLC·Filed 2022·Application pending·0 cites
- 1939US11224126B2Edge interconnects for use with circuit boards and integrated circuitsINDIANA INTEGRATED CIRCUITS LLC·Filed 2020·Granted Jan 11, 2022·0 cites·15 claims
- 2038US11488660B2Adiabatic flip-flop and memory cell designINDIANA INTEGRATED CIRCUITS LLC·Filed 2021·Granted Nov 1, 2022·0 cites·2 claims
- 2137US10182498B2Substrates with interdigitated hinged edge interconnectsINDIANA INTEGRATED CIRCUITS LLC·Filed 2016·Granted Jan 15, 2019·0 cites·9 claims
- 2234US10325875B2Edge interconnect packaging of integrated circuits for power systemsINDIANA INTEGRATED CIRCUITS LLC·Filed 2015·Granted Jun 18, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →