Inventor · disambiguated record
James Yong Meng Lee
Also filed as: LEE JAMES · LEE JAMES M Y · LEE JAMES YONG MENG
30 granted patents·2 pending applications·919 citations·filing 1999–2010
97Inventor score
Files withCHARTERED SEMICONDUCTOR MFG28GLOBALFOUNDRIES SG PTE LTD1MISHRA SHAILENDRA1UNIV SINGAPORE1WIDODO JOHNNY1
Top patents by PatentIndex Score
32 records- 0197US6300177B1Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 9, 2001·175 cites·26 claims
- 0294US6747314B2Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 8, 2004·93 cites·11 claims
- 0394US6313008B1Method to form a balloon shaped STI using a micro machining technique to remove heavily doped siliconCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·90 cites·30 claims
- 0491US6406945B1Method for forming a transistor gate dielectric with high-K and low-K regionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 18, 2002·59 cites·17 claims
- 0589US6417056B1Method to form low-overlap-capacitance transistors by forming microtrench at the gate edgeCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·51 cites·27 claims
- 0689US6306715B1Method to form smaller channel with CMOS device by isotropic etching of the gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 23, 2001·46 cites·14 claims
- 0788US6468877B1Method to form an air-gap under the edges of a gate electrode by using disposable spacer/linerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·53 cites·21 claims
- 0887US6436770B1Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·45 cites·19 claims
- 0984US6475916B1Method of patterning gate electrode with ultra-thin gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 5, 2002·37 cites·24 claims
- 1083US6709934B2Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·26 cites·10 claims
- 1182US6391720B1Process flow for a performance enhanced MOSFET with self-aligned, recessed channelCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted May 21, 2002·38 cites·50 claims
- 1278US6403484B1Method to achieve STI planarizationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·23 cites·20 claims
- 1377US7091092B2Process flow for a performance enhanced MOSFET with self-aligned, recessed channelUNIV SINGAPORE·Filed 2002·Granted Aug 15, 2006·25 cites·28 claims
- 1476US6455377B1Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)CHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 24, 2002·21 cites·35 claims
- 1573US6306741B1Method of patterning gate electrodes with high K gate dielectricsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 23, 2001·18 cites·23 claims
- 1672US6461887B1Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 8, 2002·18 cites·21 claims
- 1772US6380088B1Method to form a recessed source drain on a trench side wall with a replacement gate techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 30, 2002·19 cites·29 claims
- 1869US6303449B1Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMPCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·12 cites·11 claims
- 1966US8178417B2Method of forming shallow trench isolation structures for integrated circuitsMISHRA SHAILENDRA·Filed 2008·Granted May 15, 2012·4 cites·23 claims
- 2066US6197691B1Shallow trench isolation processCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 6, 2001·31 cites·20 claims
- 2162US6436774B1Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 20, 2002·8 cites·10 claims
- 2258US6541327B1Method to form self-aligned source/drain CMOS device on insulated staircase oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Apr 1, 2003·8 cites·9 claims
- 2354US6458717B1Methods of forming ultra-thin buffer oxide layers for gate dielectricsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 1, 2002·5 cites·30 claims
- 2452US6440800B1Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layersCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Aug 27, 2002·5 cites·12 claims
- 2552US6417054B1Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxideCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·5 cites·21 claims
- 2650US7767577B2Nested and isolated transistors with reduced impedance differenceCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Aug 3, 2010·0 cites·18 claims
- 2749US7037791B2Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gatesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted May 2, 2006·4 cites·20 claims
- 2848US7795680B2Integrated circuit system employing selective epitaxial growth technologyCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Sep 14, 2010·0 cites·20 claims
- 2947US7999300B2Memory cell structure and method for fabrication thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2009·Granted Aug 16, 2011·0 cites·22 claims
- 3044US2010102393A1Metal gate transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 3143US2006194397A1Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gatesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 3241US8143651B2Nested and isolated transistors with reduced impedance differenceWIDODO JOHNNY·Filed 2010·Granted Mar 27, 2012·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →