Inventor · disambiguated record
James A. Mccall
Also filed as: MCCALL JAMES · MCCALL JAMES A · MCCALL JAMES ALEXANDER
84 granted patents·33 pending applications·635 citations·filing 2000–2025
99Inventor score
Top patents by PatentIndex Score
117 records- 0196US6820163B1Buffering data transfer between a chipset and memory modulesINTEL CORP·Filed 2000·Granted Nov 16, 2004·118 cites·21 claims
- 0294US11776619B2Techniques to couple high bandwidth memory device on silicon substrate and package substrateTAHOE RES LTD·Filed 2023·Granted Oct 3, 2023·1 cites·20 claims
- 0394US10146711B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2016·Granted Dec 4, 2018·14 cites·27 claims
- 0493US9934842B2Multiple rank high bandwidth memoryINTEL CORP·Filed 2016·Granted Apr 3, 2018·15 cites·16 claims
- 0592US9153296B2Methods and apparatuses for dynamic memory terminationMCCALL JAMES A·Filed 2012·Granted Oct 6, 2015·14 cites·17 claims
- 0692US8972685B2Method, apparatus and system for exchanging communications via a command/address busBAINS KULJIT S·Filed 2012·Granted Mar 3, 2015·17 cites·30 claims
- 0792US8274308B2Method and apparatus for dynamic memory terminationMCCALL JAMES A·Filed 2010·Granted Sep 25, 2012·23 cites·36 claims
- 0891US9218575B2Periodic training for unmatched signal receiverINTEL CORP·Filed 2013·Granted Dec 22, 2015·14 cites·20 claims
- 0990US6366466B1Multi-layer printed circuit board with signal traces of varying widthINTEL CORP·Filed 2000·Granted Apr 2, 2002·50 cites·22 claims
- 1089US10031868B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2017·Granted Jul 24, 2018·4 cites·20 claims
- 1187US10617000B2Printed circuit board (PCB) with three-dimensional interconnects to other printed circuit boardsINTEL CORP·Filed 2017·Granted Apr 7, 2020·5 cites·26 claims
- 1287US2025006250A1Techniques to couple high bandwidth memory device on silicon substrate and package substrateTAHOE RES LTD·Filed 2024·Application pending·0 cites
- 1386US7772708B2Stacking integrated circuit diesINTEL CORP·Filed 2006·Granted Aug 10, 2010·21 cites·6 claims
- 1485US12087352B2Techniques to couple high bandwidth memory device on silicon substrate and package substrateTAHOE RES LTD·Filed 2023·Granted Sep 10, 2024·0 cites·18 claims
- 1585US6747483B2Differential memory interface systemINTEL CORP·Filed 2002·Granted Jun 8, 2004·29 cites·21 claims
- 1684US10839887B2Applying chip select for memory device identification and power management controlINTEL CORP·Filed 2017·Granted Nov 17, 2020·3 cites·22 claims
- 1784US7676917B2Method of manufacturing a circuit boardINTEL CORP·Filed 2007·Granted Mar 16, 2010·9 cites·7 claims
- 1883US10437746B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2018·Granted Oct 8, 2019·2 cites·21 claims
- 1983US9786353B2Reconfigurable clocking architectureINTEL CORP·Filed 2016·Granted Oct 10, 2017·4 cites·24 claims
- 2083US6771515B2Systems having modules with on die terminationsINTEL CORP·Filed 2001·Granted Aug 3, 2004·29 cites·23 claims
- 2182US11056179B2Techniques to couple high bandwidth memory device on silicon substrate and package substrateINTEL CORP·Filed 2020·Granted Jul 6, 2021·1 cites·16 claims
- 2282US9665527B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2014·Granted May 30, 2017·4 cites·22 claims
- 2380US8415002B2Method of manufacturing a circuit boardMCCALL JAMES A·Filed 2010·Granted Apr 9, 2013·4 cites·21 claims
- 2480US7542322B2Buffered continuous multi-drop clock ringINTEL CORP·Filed 2004·Granted Jun 2, 2009·33 cites·4 claims
- 2579US6674648B2Termination cards and systems thereforeINTEL CORP·Filed 2001·Granted Jan 6, 2004·29 cites·24 claims
- 2678US2025349327A1Stacked memory chip solution with reduced package inputs/outputs (i/os)INTEL CORP·Filed 2025·Application pending·0 cites
- 2777US10884958B2DIMM for a high bandwidth memory channelINTEL CORP·Filed 2018·Granted Jan 5, 2021·2 cites·18 claims
- 2877US7246022B2Initiation of differential link retraining upon temperature excursionINTEL CORP·Filed 2005·Granted Jul 17, 2007·11 cites·6 claims
- 2976US10541018B2DDR memory bus with a reduced data strobe signal preamble timespanINTEL CORP·Filed 2017·Granted Jan 21, 2020·2 cites·20 claims
- 3076US9595963B2Method and apparatus for dynamic memory terminationINTEL CORP·Filed 2015·Granted Mar 14, 2017·3 cites·29 claims
- 3174US7514773B2Systems and arrangements for interconnecting integrated circuit diesINTEL CORP·Filed 2006·Granted Apr 7, 2009·6 cites·14 claims
- 3273US9152257B2Low swing voltage mode driverINTEL CORP·Filed 2012·Granted Oct 6, 2015·3 cites·23 claims
- 3372US9552164B2Apparatus, method and system for determining reference voltages for a memoryINTEL CORP·Filed 2013·Granted Jan 24, 2017·4 cites·23 claims
- 3471US11557333B2Techniques to couple high bandwidth memory device on silicon substrate and package substrateTAHOE RES LTD·Filed 2021·Granted Jan 17, 2023·0 cites·18 claims
- 3571US10592445B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2018·Granted Mar 17, 2020·2 cites·31 claims
- 3670US10467160B2Memory channel having more than one DIMM per motherboard DIMM connectorINTEL CORP·Filed 2017·Granted Nov 5, 2019·1 cites·20 claims
- 3769US7447929B2Countering power resonanceINTEL CORP·Filed 2005·Granted Nov 4, 2008·8 cites·21 claims
- 3869US6700457B2Impedance compensation for circuit board breakout regionINTEL CORP·Filed 2001·Granted Mar 2, 2004·20 cites·18 claims
- 3968US8673391B2Method of manufacturing a circuit boardSHYKIND DAVID·Filed 2013·Granted Mar 18, 2014·2 cites·21 claims
- 4067US11116072B2Discrete circuit having cross-talk noise cancellation circuitry and method thereofINTEL CORP·Filed 2017·Granted Sep 7, 2021·1 cites·19 claims
- 4167US10025685B2Impedance compensation based on detecting sensor dataINTEL CORP·Filed 2015·Granted Jul 17, 2018·2 cites·22 claims
- 4267US6711027B2Modules having paths of different impedancesINTEL CORP·Filed 2001·Granted Mar 23, 2004·14 cites·29 claims
- 4365US7459200B2Circuit board designINTEL CORP·Filed 2003·Granted Dec 2, 2008·7 cites·3 claims
- 4464US12340863B2Stacked memory chip solution with reduced package inputs/outputs (I/Os)INTEL CORP·Filed 2021·Granted Jun 24, 2025·0 cites·19 claims
- 4564US10802996B2Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal linesINTEL CORP·Filed 2019·Granted Oct 13, 2020·0 cites·20 claims
- 4662US11335395B2Applying chip select for memory device identification and power management controlINTEL CORP·Filed 2020·Granted May 17, 2022·0 cites·19 claims
- 4762US10033382B2Method and apparatus for dynamic memory terminationINTEL CORP·Filed 2017·Granted Jul 24, 2018·1 cites·21 claims
- 4862US6708243B1Computer assembly with stub traces coupled to vias to add capacitance at the viasINTEL CORP·Filed 2000·Granted Mar 16, 2004·9 cites·1 claims
- 4962US2025126714A1Memory modules and socketsLI XIANG·Filed 2024·Application pending·0 cites
- 5061US9596766B2Method of manufacturing a circuit boardINTEL CORP·Filed 2014·Granted Mar 14, 2017·0 cites·7 claims
Showing the top 50 of 117 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →