Inventor · disambiguated record
Jason Z. Mo
Also filed as: MO JASON · MO JASON Z · MO JASON ZHI-CHENG
27 granted patents·4 pending applications·129 citations·filing 2005–2014
95Inventor score
Top patents by PatentIndex Score
31 records- 0188US8325723B1Method and apparatus for dynamic traffic management with packet classificationWANG CHI-LIE·Filed 2010·Granted Dec 4, 2012·12 cites·15 claims
- 0286US7447812B1Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register filesINTEGRATED DEVICE TECH·Filed 2005·Granted Nov 4, 2008·17 cites·7 claims
- 0385US7617346B2Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latencyINTEGRATED DEVICE TECH·Filed 2007·Granted Nov 10, 2009·22 cites·30 claims
- 0484US7818470B2Adaptive interrupt on serial rapid input/output (SRIO) endpointINTEGRATED DEVICE TECH·Filed 2007·Granted Oct 19, 2010·12 cites·19 claims
- 0580US8312190B2Protocol translation in a serial bufferWANG CHI-LIE·Filed 2008·Granted Nov 13, 2012·10 cites·15 claims
- 0678US8254399B1Method and apparatus for adaptive buffer management for traffic optimization on switchesWANG CHI-LIE·Filed 2009·Granted Aug 28, 2012·7 cites·10 claims
- 0777US8238339B1Method and apparatus for selective packet discardWANG CHI-LIE·Filed 2010·Granted Aug 7, 2012·5 cites·14 claims
- 0876US8320392B1Method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switchesWANG CHI-LIE·Filed 2009·Granted Nov 27, 2012·6 cites·20 claims
- 0971US7257687B2Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Aug 14, 2007·5 cites·14 claims
- 1070US8312241B2Serial buffer to support request packets with out of order response packetsWANG CHI-LIE·Filed 2008·Granted Nov 13, 2012·4 cites·20 claims
- 1170US7870313B2Method and structure to support system resource access of a serial device implementating a lite-weight protocolINTEGRATED DEVICE TECH·Filed 2007·Granted Jan 11, 2011·4 cites·28 claims
- 1270US7392354B1Multi-queue FIFO memory devices that support a backed-off standard mode of operation and methods of operating sameINTEGRATED DEVICE TECH·Filed 2005·Granted Jun 24, 2008·4 cites·5 claims
- 1368US7870310B2Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Jan 11, 2011·4 cites·20 claims
- 1467US8625621B2Method to support flexible data transport on serial protocolsWANG CHI-LIE·Filed 2008·Granted Jan 7, 2014·3 cites·17 claims
- 1566US7944876B2Time slot interchange switch with bit error rate testingINTEGRATED DEVICE TECH·Filed 2005·Granted May 17, 2011·3 cites·4 claims
- 1663US7805551B2Multi-function queue to support data offload, protocol translation and pass-through FIFOINTEGRATED DEVICE TECH·Filed 2007·Granted Sep 28, 2010·2 cites·23 claims
- 1762US8902765B1Method and apparatus for congestion and fault management with time-to-liveWANG CHI-LIE·Filed 2010·Granted Dec 2, 2014·1 cites·1 claims
- 1862US7523232B2Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Apr 21, 2009·2 cites·16 claims
- 1958US7269700B2Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Sep 11, 2007·1 cites·3 claims
- 2058US7099231B2Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Aug 29, 2006·5 cites·11 claims
- 2156US9203769B1Method and apparatus for congestion and fault management with time-to-liveINTEGRATED DEVICE TECH·Filed 2014·Granted Dec 1, 2015·0 cites·2 claims
- 2248US8213448B2Method to support lossless real time data sampling and processing on rapid I/O end-pointWANG CHI-LIE·Filed 2008·Granted Jul 3, 2012·0 cites·15 claims
- 2346US2009225775A1Serial Buffer To Support Reliable Connection Between Rapid I/O End-Point And FPGA Lite-Weight ProtocolsINTEGRATED DEVICE TECH·Filed 2008·Application pending·0 cites
- 2445US7805552B2Partial packet write and write data filtering in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Sep 28, 2010·0 cites·5 claims
- 2545US2009086750A1Non-Random Access Rapid I/O Endpoint In A Multi-Processor SystemINTEGRATED DEVICE TECH·Filed 2007·Application pending·0 cites
- 2644US2008209089A1Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor PortINTEGRATED DEVICE TECH·Filed 2007·Application pending·0 cites
- 2743US8850089B1Method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimizationWANG CHI-LIE·Filed 2010·Granted Sep 30, 2014·0 cites·6 claims
- 2840US8571050B1Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer and continuous transfer modesWANG CHI-LIE·Filed 2010·Granted Oct 29, 2013·0 cites·7 claims
- 2940US2006155940A1Multi-queue FIFO memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected FIFO memory chipsAU MARIO·Filed 2005·Application pending·0 cites
- 3034US7154327B2Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory systemINTEGRATED DEVICE TECH·Filed 2005·Granted Dec 26, 2006·0 cites·17 claims
- 3132US8230174B2Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory systemAU MARIO·Filed 2005·Granted Jul 24, 2012·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →