Inventor · disambiguated record
Jagannathan Narasimhan
Also filed as: NARASIMHAN JAGANNATHAN
12 granted patents·1 pending application·134 citations·filing 1997–2013
89Inventor score
Top patents by PatentIndex Score
13 records- 0193US8271920B2Converged large block and structured synthesis for high performance microprocessor designsCHO MINSIK·Filed 2010·Granted Sep 18, 2012·34 cites·22 claims
- 0282US7571411B2Methods and apparatus for providing flexible timing-driven routing treesIBM·Filed 2006·Granted Aug 4, 2009·20 cites·1 claims
- 0370US6061508AModeling and processing of on-chip interconnect capacitanceIBM·Filed 1997·Granted May 9, 2000·60 cites·42 claims
- 0462US6611945B1Method for propagating switching activity information in digital combinatorial networksIBM·Filed 2000·Granted Aug 26, 2003·11 cites·35 claims
- 0561US8407652B2Task-based multi-process design synthesisDRUMM ANTHONY D·Filed 2010·Granted Mar 26, 2013·1 cites·23 claims
- 0659US8341565B2Task-based multi-process design synthesis with reproducible transformsDRUMM ANTHONY D·Filed 2010·Granted Dec 25, 2012·1 cites·23 claims
- 0758US8392866B2Task-based multi-process design synthesis with notification of transform signaturesDRUMM ANTHONY D·Filed 2010·Granted Mar 5, 2013·1 cites·25 claims
- 0858US8095904B2Methods and apparatus for providing flexible timing-driven routing treesHENTSCHKE RENATO FERNANDES·Filed 2008·Granted Jan 10, 2012·4 cites·18 claims
- 0953US8677304B2Task-based multi-process design synthesisIBM·Filed 2013·Granted Mar 18, 2014·0 cites·25 claims
- 1052US7469395B2Wiring optimizations for powerIBM·Filed 2007·Granted Dec 23, 2008·0 cites·24 claims
- 1152US6985004B2Wiring optimizations for powerIBM·Filed 2001·Granted Jan 10, 2006·2 cites·20 claims
- 1248US7346875B2Wiring optimizations for powerIBM·Filed 2005·Granted Mar 18, 2008·0 cites·11 claims
- 1342US2007204255A1Net routingIBM·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →