Inventor · disambiguated record
Jayanthi Pallinti
Also filed as: PALLINTI JAYANTHI
19 granted patents·8 pending applications·215 citations·filing 1998–2024
95Inventor score
Top patents by PatentIndex Score
27 records- 0186US6417093B1Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizingLSI LOGIC CORP·Filed 2000·Granted Jul 9, 2002·52 cites·23 claims
- 0277US6391768B1Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structureLSI LOGIC CORP·Filed 2000·Granted May 21, 2002·28 cites·2 claims
- 0376US7205673B1Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processingLSI LOGIC CORP·Filed 2005·Granted Apr 17, 2007·7 cites·3 claims
- 0476US6752916B1Electrochemical planarization end point detectionLSI LOGIC CORP·Filed 2002·Granted Jun 22, 2004·10 cites·14 claims
- 0575US6607967B1Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrateLSI LOGIC CORP·Filed 2000·Granted Aug 19, 2003·19 cites·16 claims
- 0672US8552560B2Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processingBHATT HEMANSHU·Filed 2005·Granted Oct 8, 2013·7 cites·3 claims
- 0772US6503828B1Process for selective polishing of metal-filled trenches of integrated circuit structuresLSI LOGIC CORP·Filed 2001·Granted Jan 7, 2003·21 cites·31 claims
- 0870US7531442B2Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processingLSI CORP·Filed 2005·Granted May 12, 2009·5 cites·4 claims
- 0962US6489242B1Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structuresLSI LOGIC CORP·Filed 2000·Granted Dec 3, 2002·7 cites·2 claims
- 1061US6424019B1Shallow trench isolation chemical-mechanical polishing processLSI LOGIC CORP·Filed 2000·Granted Jul 23, 2002·9 cites·4 claims
- 1159US2025029952A1Systems and methods for connecting integrated circuitsAVAGO TECH INT SALES PTE LID·Filed 2023·Application pending·0 cites
- 1258US6838379B1Process for reducing impurity levels, stress, and resistivity, and increasing grain size of copper filler in trenches and vias of integrated circuit structures to enhance electrical performance of copper fillerLSI LOGIC CORP·Filed 2003·Granted Jan 4, 2005·9 cites·16 claims
- 1357US6555475B1Arrangement and method for polishing a surface of a semiconductor waferLSI LOGIC CORP·Filed 2002·Granted Apr 29, 2003·6 cites·12 claims
- 1457US6060370AMethod for shallow trench isolations with chemical-mechanical polishingLSI LOGIC CORP·Filed 1998·Granted May 9, 2000·20 cites·17 claims
- 1556US6439981B1Arrangement and method for polishing a surface of a semiconductor waferLSI LOGIC CORP·Filed 2000·Granted Aug 27, 2002·6 cites·8 claims
- 1656US2025364474A1Barriers in seminconductor devicesAVAGO TECH INT SALES PTE LID·Filed 2024·Application pending·0 cites
- 1753US6372524B1Method for CMP endpoint detectionLSI LOGIC CORP·Filed 2001·Granted Apr 16, 2002·4 cites·20 claims
- 1852US2025046622A1Hybrid substrates and manufacturing methods thereofAVAGO TECH INT SALES PTE LID·Filed 2023·Application pending·0 cites
- 1952US2025046690A1Hybrid substrates and manufacturing methods thereofAVAGO TECH INT SALES PTE LID·Filed 2023·Application pending·0 cites
- 2050US2014030541A1Alternate pad structures/passivation integration schemes to reduce or eliminate imc cracking in post wire bonded dies during cu/low-k beol processingLSI CORP·Filed 2013·Application pending·0 cites
- 2149US6586326B2Metal planarization systemLSI LOGIC CORP·Filed 2001·Granted Jul 1, 2003·3 cites·6 claims
- 2247US6713394B2Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structuresLSI LOGIC CORP·Filed 2002·Granted Mar 30, 2004·1 cites·17 claims
- 2345US6951808B2Metal planarization systemLSI LOGIC CORP·Filed 2003·Granted Oct 4, 2005·1 cites·11 claims
- 2440US8076779B2Reduction of macro level stresses in copper/low-K wafersSUN SEY-SHING·Filed 2005·Granted Dec 13, 2011·0 cites·4 claims
- 2539US2005224358A1Method for improved local planarity control during electropolishingLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 2635US2010244276A1Three-dimensional electronics packageLSI CORP·Filed 2010·Application pending·0 cites
- 2735US2004207093A1Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnectsFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →