Inventor · disambiguated record
Jack D. Parrish
Also filed as: PARRISH JACK · PARRISH JACK D · PARRISH JACK DUANE
6 granted patents·305 citations·filing 1989–2011
85Inventor score
Top patents by PatentIndex Score
6 records- 0192US5047358AProcess for forming high and low voltage CMOS transistors on a single integrated circuit chipDELCO ELECTRONICS CORP·Filed 1989·Granted Sep 10, 1991·116 cites·5 claims
- 0292US4918026AProcess for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chipDELCO ELECTRONICS CORP·Filed 1989·Granted Apr 17, 1990·115 cites·11 claims
- 0382US5366916AMethod of making a high voltage implanted channel device for VLSI and ULSI processesDELCO ELECTRONICS CORP·Filed 1993·Granted Nov 22, 1994·61 cites·12 claims
- 0459US8631905B2Ladder apparatusPARRISH JACK·Filed 2011·Granted Jan 21, 2014·4 cites·20 claims
- 0537US5734186ACMOS voltage clampDELCO ELECTRONICS CORP·Filed 1996·Granted Mar 31, 1998·5 cites·9 claims
- 0634US5869366AMethod for forming voltage clamp having a breakdown voltage of 40 VdcDELCO ELECTRONICS CORP·Filed 1997·Granted Feb 9, 1999·4 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →