Inventor · disambiguated record
James H. Pomerene
Also filed as: POMERENE JAMES H
20 granted patents·1,584 citations·filing 1979–1993
97Inventor score
Technology areasG06F
Files withIBM20
Top patents by PatentIndex Score
20 records- 0195US4295193AMachine for multiple instruction executionIBM·Filed 1979·Granted Oct 13, 1981·113 cites·6 claims
- 0294US4903196AMethod and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessorIBM·Filed 1986·Granted Feb 20, 1990·191 cites·20 claims
- 0391US4807110APrefetching system for a cache having a second directory for sequentially accessed blocksIBM·Filed 1984·Granted Feb 21, 1989·106 cites·17 claims
- 0490US4991080APipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructionsIBM·Filed 1986·Granted Feb 5, 1991·122 cites·18 claims
- 0589US5434985ASimultaneous prediction of multiple branches for superscalar processingIBM·Filed 1992·Granted Jul 18, 1995·139 cites·27 claims
- 0688US5155831AData processing system with fast queue store interposed between store-through caches and a main memoryIBM·Filed 1989·Granted Oct 13, 1992·102 cites·11 claims
- 0788US4679141APageable branch history tableIBM·Filed 1985·Granted Jul 7, 1987·107 cites·7 claims
- 0886US4437149ACache memory architecture with decodingIBM·Filed 1980·Granted Mar 13, 1984·74 cites·11 claims
- 0985US4943908AMultiple branch analyzer for prefetching cache linesIBM·Filed 1987·Granted Jul 24, 1990·87 cites·9 claims
- 1082US4774654AApparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memoryIBM·Filed 1984·Granted Sep 27, 1988·59 cites·10 claims
- 1180US5210831AMethods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locationsIBM·Filed 1989·Granted May 11, 1993·65 cites·9 claims
- 1279US4991090APosting out-of-sequence fetchesIBM·Filed 1987·Granted Feb 5, 1991·61 cites·9 claims
- 1378US4823259AHigh speed buffer store arrangement for quick wide transfer of dataIBM·Filed 1988·Granted Apr 18, 1989·66 cites·2 claims
- 1478US4763245ABranch prediction mechanism in which a branch history table is updated using an operand sensitive branch tableIBM·Filed 1985·Granted Aug 9, 1988·62 cites·12 claims
- 1570US5291442AMethod and apparatus for dynamic cache line sectoring in multiprocessor systemsIBM·Filed 1990·Granted Mar 1, 1994·53 cites·17 claims
- 1669US5197139ACache management for multi-processor systems utilizing bulk cross-invalidateIBM·Filed 1990·Granted Mar 23, 1993·52 cites·7 claims
- 1765US5276882ASubroutine return through branch history tableIBM·Filed 1990·Granted Jan 4, 1994·47 cites·5 claims
- 1865US5233702ACache miss facility with stored sequences for data fetchingIBM·Filed 1989·Granted Aug 3, 1993·32 cites·13 claims
- 1956US5297281AMultiple sequence processor systemIBM·Filed 1992·Granted Mar 22, 1994·30 cites·11 claims
- 2044US5584002ACache remapping using synonym classesIBM·Filed 1993·Granted Dec 10, 1996·16 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →