Inventor · disambiguated record
Jayakrishna P S
Also filed as: S JAYAKRISHNA · S JAYAKRISHNA P
5 granted patents·8 pending applications·18 citations·filing 2010–2024
78Inventor score
Top patents by PatentIndex Score
13 records- 0197US12079155B2Graphics processor operation scheduling for deterministic latencyINTEL CORP·Filed 2020·Granted Sep 3, 2024·6 cites·20 claims
- 0292US2025103546A1Cache structure and utilizationINTEL CORP·Filed 2024·Application pending·0 cites
- 0391US2024403259A1Compression techniquesINTEL CORP·Filed 2024·Application pending·0 cites
- 0491US2025028675A1Graphics processor operation scheduling for deterministic latencyINTEL CORP·Filed 2024·Application pending·0 cites
- 0590US2024411717A1Cache structure and utilizationINTEL CORP·Filed 2024·Application pending·0 cites
- 0683US12093210B2Compression techniquesINTEL CORP·Filed 2020·Granted Sep 17, 2024·1 cites·18 claims
- 0782US8782461B2Method and system of live error recoveryMUTHRASANALLUR SRIDHAR·Filed 2010·Granted Jul 15, 2014·11 cites·22 claims
- 0881US12153541B2Cache structure and utilizationINTEL CORP·Filed 2022·Granted Nov 26, 2024·0 cites·18 claims
- 0954US2025335356A1Auxiliary compression control surface access in a multi-node memory systemINTEL CORP·Filed 2024·Application pending·0 cites
- 1053US2025310271A1Method and apparatus for management of credits in a credit-based fabricINTEL CORP·Filed 2024·Application pending·0 cites
- 1150US2024311298A1Configuration independent surface layout for data processingINTEL CORP·Filed 2023·Application pending·0 cites
- 1249US2023038862A1Techniques for multi-source to multi-destination weighted round robin arbitrationINTEL CORP·Filed 2022·Application pending·0 cites
- 1347US9471323B2System and method of using an atomic data buffer to bypass a memory locationINTEL CORP·Filed 2013·Granted Oct 18, 2016·0 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →