Inventor · disambiguated record
Jagadeesh Sankaran
Also filed as: SANKARAN JAGADEESH
39 granted patents·15 pending applications·419 citations·filing 2001–2024
97Inventor score
Top patents by PatentIndex Score
54 records- 0195US6876317B2Method of context based adaptive binary arithmetic decoding with two part symbol decodingTEXAS INSTRUMENTS INC·Filed 2004·Granted Apr 5, 2005·123 cites·3 claims
- 0294US7813567B2Method of CABAC significance MAP decoding suitable for use on VLIW data processorsTEXAS INSTRUMENTS INC·Filed 2007·Granted Oct 12, 2010·45 cites·15 claims
- 0393US11704067B2Performing multiple point table lookups in a single cycle in a system on chipNVIDIA CORP·Filed 2021·Granted Jul 18, 2023·6 cites·20 claims
- 0493US11593290B1Using a hardware sequencer in a direct memory access system of a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 28, 2023·4 cites·20 claims
- 0593US11573921B1Built-in self-test for a programmable vision accelerator of a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 7, 2023·5 cites·20 claims
- 0693US11573795B1Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 7, 2023·6 cites·20 claims
- 0793US7885473B2Method of CABAC coefficient magnitude and sign decoding suitable for use on VLIW data processorsTEXAS INSTRUMENTS INC·Filed 2007·Granted Feb 8, 2011·34 cites·15 claims
- 0892US11636063B2Hardware accelerated anomaly detection using a min/max collector in a system on a chipNVIDIA CORP·Filed 2021·Granted Apr 25, 2023·5 cites·20 claims
- 0991US9519617B2Processor with instruction variable data distributionHUNG CHING-YU·Filed 2012·Granted Dec 13, 2016·20 cites·12 claims
- 1090US10803009B2Processor with table lookup processing unitHUNG CHING YU·Filed 2012·Granted Oct 13, 2020·17 cites·8 claims
- 1188US11934829B2Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chipNVIDIA CORP·Filed 2022·Granted Mar 19, 2024·1 cites·20 claims
- 1288US7457362B2Loop deblock filtering of block coded video in a very long instruction word processorTEXAS INSTRUMENTS INC·Filed 2004·Granted Nov 25, 2008·49 cites·4 claims
- 1387US12093539B2Using per memory bank load caches for reducing power use in a system on a chipNVIDIA CORP·Filed 2022·Granted Sep 17, 2024·1 cites·20 claims
- 1486US7176815B1Video coding with CABACTEXAS INSTRUMENTS INC·Filed 2005·Granted Feb 13, 2007·15 cites·4 claims
- 1582US11630800B2Programmable vision acceleratorNVIDIA CORP·Filed 2016·Granted Apr 18, 2023·5 cites·21 claims
- 1681US11836527B2Accelerating table lookups using a decoupled lookup table accelerator in a system on a chipNVIDIA CORP·Filed 2021·Granted Dec 5, 2023·1 cites·20 claims
- 1781US11593001B1Using per memory bank load caches for reducing power use in a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 28, 2023·1 cites·20 claims
- 1881US7788642B2Displaying cache information using mark-up techniquesTEXAS INSTRUMENTS INC·Filed 2006·Granted Aug 31, 2010·11 cites·17 claims
- 1977US8707013B2On-demand predicate registersSANKARAN JAGADEESH·Filed 2010·Granted Apr 22, 2014·6 cites·4 claims
- 2077US2025103529A1Using a hardware sequencer in a direct memory access system of a system on a chipNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2176US7376813B2Register move instruction for section select of source operandTEXAS INSTRUMENTS INC·Filed 2005·Granted May 20, 2008·10 cites·29 claims
- 2274US7177876B2Speculative load of look up table entries based upon coarse index calculation in parallel with fine index calculationTEXAS INSTRUMENTS INC·Filed 2005·Granted Feb 13, 2007·8 cites·42 claims
- 2373US12204475B2Using a hardware sequencer in a direct memory access system of a system on a chipNVIDIA CORP·Filed 2022·Granted Jan 21, 2025·0 cites·20 claims
- 2473US2024134645A1Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chipNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2572US2023049454A1Processor with table lookup unitTEXAS INSTRUMENTS INC·Filed 2022·Application pending·0 cites
- 2670US12050548B2Built-in self-test for a programmable vision accelerator of a system on a chipNVIDIA CORP·Filed 2022·Granted Jul 30, 2024·0 cites·20 claims
- 2770US11940947B2Hardware accelerated anomaly detection using a min/max collector in a system on a chipNVIDIA CORP·Filed 2023·Granted Mar 26, 2024·0 cites·20 claims
- 2869US2024265555A1Object detection using image alignment for autonomous machine applicationsNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2968US11468003B2Vector table load instruction with address generation field to access table offset valueTEXAS INSTRUMENTS INC·Filed 2020·Granted Oct 11, 2022·0 cites·20 claims
- 3068US8706923B2Methods and systems for direct memory access (DMA) in-flight statusSANKARAN JAGADEESH·Filed 2010·Granted Apr 22, 2014·3 cites·11 claims
- 3165US7673294B2Mechanism for pipelining loops with irregular loop controlTEXAS INSTRUMENTS INC·Filed 2006·Granted Mar 2, 2010·4 cites·4 claims
- 3264US6940429B2Method of context based adaptive binary arithmetic encoding with decoupled range re-normalization and bit insertionTEXAS INSTRUMENTS INC·Filed 2004·Granted Sep 6, 2005·13 cites·7 claims
- 3363US7391915B1Cache friendly method for performing inverse discrete wavelet transformTEXAS INSTRUMENTS INC·Filed 2005·Granted Jun 24, 2008·3 cites·7 claims
- 3462US7779206B2Cache inspection with inspection bypass featureTEXAS INSTRUMENTS INC·Filed 2006·Granted Aug 17, 2010·2 cites·19 claims
- 3562US7739453B2Providing information associated with a cacheTEXAS INSTRUMENTS INC·Filed 2006·Granted Jun 15, 2010·2 cites·22 claims
- 3660US11961243B2Object detection using image alignment for autonomous machine applicationsNVIDIA CORP·Filed 2021·Granted Apr 16, 2024·0 cites·31 claims
- 3759US6735737B2Error correction structures and methodsTEXAS INSTRUMENTS INC·Filed 2001·Granted May 11, 2004·11 cites·2 claims
- 3855US7458007B2Error correction structures and methodsTEXAS INSTRUMENTS INC·Filed 2001·Granted Nov 25, 2008·8 cites·5 claims
- 3952US12118353B2Performing load and permute with a single instruction in a system on a chipNVIDIA CORP·Filed 2021·Granted Oct 15, 2024·0 cites·20 claims
- 4052US12099439B2Performing load and store operations of 2D arrays in a single cycle in a system on a chipNVIDIA CORP·Filed 2021·Granted Sep 24, 2024·0 cites·20 claims
- 4150US11954496B2Reduced memory write requirements in a system on a chip using automatic store predicationNVIDIA CORP·Filed 2021·Granted Apr 9, 2024·0 cites·20 claims
- 4247US2009006665A1Modified Memory Architecture for CODECS With Multiple CPUsSANKARAN JAGADEESH·Filed 2008·Application pending·0 cites
- 4346US2005058358A1Method for planar processing of wavelet zero-tree dataFiled 2004·Application pending·0 cites
- 4445US2009006037A1Accurate Benchmarking of CODECS With Multiple CPUsSANKARAN JAGADEESH·Filed 2008·Application pending·0 cites
- 4544US9336454B2Vector processor calculation of local binary patternsTEXAS INSTRUMENTS INC·Filed 2013·Granted May 10, 2016·0 cites·16 claims
- 4643US7721054B2Speculative data loading using circular addressing or simulated circular addressingTEXAS INSTRUMENTS INC·Filed 2006·Granted May 18, 2010·0 cites·5 claims
- 4743US2009006664A1Linked DMA Transfers in Video CODECSSANKARAN JAGADEESH·Filed 2008·Application pending·0 cites
- 4843US2023130478A1Hybrid solution for stereo imagingNVIDIA CORP·Filed 2020·Application pending·0 cites
- 4943US2023050062A1Simd data path organization to increase processing throughput in a system on a chipNVIDIA CORP·Filed 2021·Application pending·0 cites
- 5041US2006259696A1Determining differences between cached copies of an addressTEXAS INSTRUMENTS INC·Filed 2006·Application pending·0 cites
Showing the top 50 of 54 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →