Inventor · disambiguated record
Jayesh V. Sheth
Also filed as: SHETH JAYESH V · SHETH JAYESH VRAJLAL
17 granted patents·610 citations·filing 1983–1997
95Inventor score
Top patents by PatentIndex Score
17 records- 0180US5511224AConfigurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memoriesUNISYS CORP·Filed 1995·Granted Apr 23, 1996·101 cites·19 claims
- 0279US5386517ADual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speedsUNISYS CORP·Filed 1993·Granted Jan 31, 1995·89 cites·12 claims
- 0370US4542457ABurst mode data block transfer systemBURROUGHS CORP·Filed 1983·Granted Sep 17, 1985·40 cites·8 claims
- 0469US4607348ATransfer rate control system from tape peripheral to buffer memory of peripheral controllerBURROUGHS CORP·Filed 1985·Granted Aug 19, 1986·41 cites·15 claims
- 0568US4644463ASystem for regulating data transfer operationsBURROUGHS CORP·Filed 1985·Granted Feb 17, 1987·44 cites·15 claims
- 0667US4602331AMagnetic tape-data link processor providing automatic data transferBURROUGHS CORP·Filed 1983·Granted Jul 22, 1986·33 cites·4 claims
- 0763US5519883AInterbus interface moduleUNISYS CORP·Filed 1993·Granted May 21, 1996·42 cites·15 claims
- 0859US5696937ACache controller utilizing a state machine for controlling invalidations in a network with dual system bussesUNISYS CORP·Filed 1995·Granted Dec 9, 1997·39 cites·6 claims
- 0959US5666515AInformation processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked addressUNISYS CORP·Filed 1996·Granted Sep 9, 1997·38 cites·1 claims
- 1055US5293621AVarying wait interval retry apparatus and method for preventing bus lockoutUNISYS CORP·Filed 1993·Granted Mar 8, 1994·28 cites·25 claims
- 1153US5809533ADual bus system with multiple processors having data coherency maintenanceUNISYS CORP·Filed 1997·Granted Sep 15, 1998·29 cites·7 claims
- 1250US4616337AAutomatic read system for peripheral-controllerBURROUGHS CORP·Filed 1983·Granted Oct 7, 1986·17 cites·7 claims
- 1350US4613954ABlock counter system to monitor data transfersBURROUGHS CORP·Filed 1985·Granted Sep 23, 1986·18 cites·14 claims
- 1449US5737756ADual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queueUNISYS CORP·Filed 1996·Granted Apr 7, 1998·24 cites·2 claims
- 1545US4534013AAutomatic write system for peripheral-controllerBURROUGHS CORP·Filed 1983·Granted Aug 6, 1985·14 cites·6 claims
- 1640US5293496AInhibit write apparatus and method for preventing bus lockoutUNISYS CORP·Filed 1993·Granted Mar 8, 1994·12 cites·12 claims
- 1730US5349620ATimer access control apparatusUNISYS CORP·Filed 1993·Granted Sep 20, 1994·1 cites·8 claims
Join the waitlist — get patent alerts
Get an alert when Jayesh V. Sheth files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →