Inventor · disambiguated record
Javier Soto Gonzalez
Also filed as: SOTO GONZALEZ JAVIER
23 granted patents·3 pending applications·31 citations·filing 2013–2024
92Inventor score
Top patents by PatentIndex Score
26 records- 0193US9505607B2Methods of forming sensor integrated packages and structures formed therebyINTEL CORP·Filed 2015·Granted Nov 29, 2016·8 cites·22 claims
- 0287US11101222B2Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layersINTEL CORP·Filed 2016·Granted Aug 24, 2021·4 cites·25 claims
- 0385US10872872B2Package substrate with high-density interconnect layer having pillar and via connections for fan out scalingINTEL CORP·Filed 2016·Granted Dec 22, 2020·4 cites·17 claims
- 0485US2025125277A1Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layersINTEL CORP·Filed 2024·Application pending·0 cites
- 0582US11532584B2Package substrate with high-density interconnect layer having pillar and via connections for fan out scalingINTEL CORP·Filed 2020·Granted Dec 20, 2022·1 cites·18 claims
- 0681US12218071B2Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layersINTEL CORP·Filed 2023·Granted Feb 4, 2025·0 cites·28 claims
- 0781US2025096197A1Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making sameINTEL CORP·Filed 2024·Application pending·0 cites
- 0877US9832860B2Panel level fabrication of package substrates with integrated stiffenersINTEL CORP·Filed 2014·Granted Nov 28, 2017·4 cites·15 claims
- 0975US10978399B2Die interconnect substrate, an electrical device, and a method for forming a die interconnect substrateINTEL CORP·Filed 2017·Granted Apr 13, 2021·2 cites·25 claims
- 1074US11735531B2Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layersINTEL CORP·Filed 2021·Granted Aug 22, 2023·0 cites·5 claims
- 1174US10204855B2Bendable and stretchable electronic devices and methodsINTEL CORP·Filed 2014·Granted Feb 12, 2019·3 cites·5 claims
- 1270US9780054B2Semiconductor package with embedded die and its methods of fabricationINTEL CORP·Filed 2014·Granted Oct 3, 2017·2 cites·13 claims
- 1369US12199067B2Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making sameINTEL CORP·Filed 2021·Granted Jan 14, 2025·0 cites·17 claims
- 1469US12002745B2High performance integrated RF passives using dual lithography processINTEL CORP·Filed 2021·Granted Jun 4, 2024·0 cites·5 claims
- 1568US10971453B2Semiconductor packaging with high density interconnectsINTEL CORP·Filed 2016·Granted Apr 6, 2021·1 cites·20 claims
- 1666US10410939B2Package power delivery using plane and shaped viasINTEL CORP·Filed 2015·Granted Sep 10, 2019·1 cites·25 claims
- 1765US11881457B2Semiconductor packaging with high density interconnectsTAHOE RES LTD·Filed 2021·Granted Jan 23, 2024·0 cites·19 claims
- 1860US10798817B2Method for making a flexible wearable circuitINTEL CORP·Filed 2015·Granted Oct 6, 2020·1 cites·19 claims
- 1959US10971416B2Package power delivery using plane and shaped viasINTEL CORP·Filed 2019·Granted Apr 6, 2021·0 cites·16 claims
- 2055US11004824B2Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making sameINTEL CORP·Filed 2016·Granted May 11, 2021·0 cites·24 claims
- 2152US9691727B2Pad-less interconnect for electrical coreless substrateINTEL CORP·Filed 2015·Granted Jun 27, 2017·0 cites·19 claims
- 2252US9165914B2Forming die backside coating structures with coreless packagesINTEL CORP·Filed 2013·Granted Oct 20, 2015·0 cites·12 claims
- 2351US12068172B2Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packagesINTEL CORP·Filed 2019·Granted Aug 20, 2024·0 cites·13 claims
- 2449US11227825B2High performance integrated RF passives using dual lithography processINTEL CORP·Filed 2015·Granted Jan 18, 2022·0 cites·9 claims
- 2546US10327330B2Stretchable electronic assemblyINTEL CORP·Filed 2015·Granted Jun 18, 2019·0 cites·18 claims
- 2636US2017344055A1Structural brace for electronic circuit with stretchable substrateINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →