Inventor · disambiguated record
Jason Steill
Also filed as: STEILL JASON · STEILL JASON SCOTT
1 granted patent·12 pending applications·0 citations·filing 2020–2023
6Inventor score
Technology areasH10W
Top patents by PatentIndex Score
13 records- 0153US2025006616A1Hybrid metallization surfaces for integrated circuit packagesINTEL CORP·Filed 2023·Application pending·0 cites
- 0252US2024222035A1Package substrate embedded multi-layered in via capacitorsINTEL CORP·Filed 2022·Application pending·0 cites
- 0351US2024113048A1Integrated horizontal varistor on glass core for voltage regulationINTEL CORP·Filed 2022·Application pending·0 cites
- 0451US2025006614A1Intervening layers for thru-via seed metallizationSHANMUGAM RENGARAJAN·Filed 2023·Application pending·0 cites
- 0550US2024006299A1Sinx based surface finish architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 0650US2024006291A1Pocketed copper in first layer interconnect and methodINTEL CORP·Filed 2022·Application pending·0 cites
- 0750US2024113046A1Embedded thin film varistor in through glass viasINTEL CORP·Filed 2022·Application pending·0 cites
- 0849US2024188222A1Method of forming a package substrateINTEL CORP·Filed 2022·Application pending·0 cites
- 0949US2024006298A1Substrate having one or more electrical interconnectsINTEL CORP·Filed 2022·Application pending·0 cites
- 1048US12033930B2Selectively roughened copper architectures for low insertion loss conductive featuresINTEL CORP·Filed 2020·Granted Jul 9, 2024·0 cites·18 claims
- 1147US2023420346A1Single lithography methods for interconnect architecturesINTEL CORP·Filed 2022·Application pending·0 cites
- 1246US2023420298A1Multi-pathway routing via through holeINTEL CORP·Filed 2022·Application pending·0 cites
- 1346US2023420353A1Asymmetrical dielectric-to-metal adhesion architecture for electronic packagesINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →