Inventor · disambiguated record
Jay J. Sturges
Also filed as: STURGES JAY · STURGES JAY J
14 granted patents·681 citations·filing 1992–2000
95Inventor score
Top patents by PatentIndex Score
14 records- 0194US5854637AMethod and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controllerINTEL CORP·Filed 1995·Granted Dec 29, 1998·138 cites·17 claims
- 0286US5491666AApparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereofINTEL CORP·Filed 1995·Granted Feb 13, 1996·58 cites·12 claims
- 0383US5930827AMethod and apparatus for dynamic memory management by association of free memory blocks using a binary tree organized in an address and size dependent mannerINTEL CORP·Filed 1996·Granted Jul 27, 1999·110 cites·31 claims
- 0475US6222564B1Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controllerINTEL CORP·Filed 1998·Granted Apr 24, 2001·38 cites·21 claims
- 0574US5371495ADeterministic routing method for minimal switch circuitsINTEL CORP·Filed 1992·Granted Dec 6, 1994·56 cites·13 claims
- 0672US5333139AMethod of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chainINTEL CORP·Filed 1992·Granted Jul 26, 1994·33 cites·5 claims
- 0771US6138273AProgrammable interpretive virtual machineINTEL CORP·Filed 1994·Granted Oct 24, 2000·54 cites·18 claims
- 0871US5761537AMethod and apparatus for integrating three dimensional sound into a computer system having a stereo audio circuitINTEL CORP·Filed 1995·Granted Jun 2, 1998·57 cites·18 claims
- 0965US5448525AApparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereofINTEL CORP·Filed 1994·Granted Sep 5, 1995·22 cites·5 claims
- 1064US5742793AMethod and apparatus for dynamic memory management by association of free memory blocks using a binary tree organized in an address and size dependent mannerINTEL CORP·Filed 1994·Granted Apr 21, 1998·53 cites·18 claims
- 1160US5490266AProcess oriented logic simulation having stability checkingALTERA CORP·Filed 1994·Granted Feb 6, 1996·36 cites·13 claims
- 1259US7356809B1Programmable interpretive virtual machineINTEL CORP·Filed 2000·Granted Apr 8, 2008·7 cites·19 claims
- 1339US5572198AMethod and apparatus for routing in reduced switch matrices to provide one hundred percent coverageINTEL CORP·Filed 1994·Granted Nov 5, 1996·8 cites·30 claims
- 1437US5530439ADeterministic method and an apparatus for minimal switch circuitsINTEL CORP·Filed 1994·Granted Jun 25, 1996·11 cites·31 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →