Inventor · disambiguated record
Jean Audet
Also filed as: AUDET JEAN · AUDET JEAN J
37 granted patents·174 citations·filing 2000–2020
97Inventor score
Top patents by PatentIndex Score
37 records- 0192US10784202B2High-density chip-to-chip interconnection with silicon bridgeIBM·Filed 2017·Granted Sep 22, 2020·33 cites·15 claims
- 0292US9443799B2Interposer with lattice construction and embedded conductive metal structuresIBM·Filed 2014·Granted Sep 13, 2016·9 cites·8 claims
- 0391US11209598B2Photonics package with face-to-face bondingIBM·Filed 2019·Granted Dec 28, 2021·11 cites·19 claims
- 0491US7268570B1Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chipIBM·Filed 2006·Granted Sep 11, 2007·24 cites·20 claims
- 0589US9553079B1Flip chip assembly with connected componentIBM·Filed 2015·Granted Jan 24, 2017·7 cites·5 claims
- 0688US9673064B2Interposer with lattice construction and embedded conductive metal structuresIBM·Filed 2015·Granted Jun 6, 2017·4 cites·16 claims
- 0786US7420378B2Power grid structure to optimize performance of a multiple core processorIBM·Filed 2006·Granted Sep 2, 2008·12 cites·8 claims
- 0881US10211174B2Flip chip assembly with connected componentIBM·Filed 2017·Granted Feb 19, 2019·3 cites·4 claims
- 0978US10622299B2Multi terminal capacitor within input output path of semiconductor package interconnectIBM·Filed 2019·Granted Apr 14, 2020·1 cites·20 claims
- 1078US7454833B2High performance chip carrier substrateIBM·Filed 2007·Granted Nov 25, 2008·6 cites·7 claims
- 1171US10460956B2Interposer with lattice construction and embedded conductive metal structuresIBM·Filed 2016·Granted Oct 29, 2019·1 cites·17 claims
- 1271US8841209B2Method for forming coreless flip chip ball grid array (FCBGA) substrates and such substrates formed by the methodALLARD SYLVIE·Filed 2011·Granted Sep 23, 2014·4 cites·14 claims
- 1368US11388821B2Thin film capacitors for core and adjacent build up layersIBM·Filed 2020·Granted Jul 12, 2022·0 cites·13 claims
- 1468US7667470B2Power grid structure to optimize performance of a multiple core processorIBM·Filed 2008·Granted Feb 23, 2010·3 cites·12 claims
- 1568US7482180B1Method for determining the impact of layer thicknesses on laminate warpageIBM·Filed 2008·Granted Jan 27, 2009·3 cites·1 claims
- 1667US6762367B2Electronic package having high density signal wires with low resistanceIBM·Filed 2002·Granted Jul 13, 2004·13 cites·26 claims
- 1765US7863526B2High performance chip carrier substrateIBM·Filed 2008·Granted Jan 4, 2011·2 cites·18 claims
- 1864US7214886B2High performance chip carrier substrateIBM·Filed 2003·Granted May 8, 2007·7 cites·3 claims
- 1962US10949600B2Semiconductor package floating metal checksIBM·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 2062US10660209B2Thin film capacitors for core and adjacent build up layersIBM·Filed 2017·Granted May 19, 2020·0 cites·8 claims
- 2162US7868459B2Semiconductor package having non-aligned active viasIBM·Filed 2006·Granted Jan 11, 2011·2 cites·7 claims
- 2261US10224274B2Multi terminal capacitor within input output path of semiconductor package interconnectIBM·Filed 2017·Granted Mar 5, 2019·0 cites·16 claims
- 2361US7312523B2Enhanced via structure for organic module performanceIBM·Filed 2005·Granted Dec 25, 2007·2 cites·20 claims
- 2460US10224273B2Multi terminal capacitor within input output path of semiconductor package interconnectIBM·Filed 2017·Granted Mar 5, 2019·0 cites·10 claims
- 2560US7017128B2Concurrent electrical signal wiring optimization for an electronic packageIBM·Filed 2003·Granted Mar 21, 2006·8 cites·9 claims
- 2660US6703706B2Concurrent electrical signal wiring optimization for an electronic packageIBM·Filed 2002·Granted Mar 9, 2004·8 cites·17 claims
- 2758US9899313B2Multi terminal capacitor within input output path of semiconductor package interconnectIBM·Filed 2016·Granted Feb 20, 2018·0 cites·19 claims
- 2858US7786579B2Apparatus for crack prevention in integrated circuit packagesIBM·Filed 2007·Granted Aug 31, 2010·1 cites·4 claims
- 2957US7066740B2Area array package with low inductance connecting deviceIBM·Filed 2003·Granted Jun 27, 2006·7 cites·25 claims
- 3056US10423751B2Semiconductor package floating metal checksIBM·Filed 2017·Granted Sep 24, 2019·0 cites·20 claims
- 3153US10813215B2Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performanceIBM·Filed 2016·Granted Oct 20, 2020·0 cites·16 claims
- 3253US10687420B2Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performanceIBM·Filed 2016·Granted Jun 16, 2020·0 cites·11 claims
- 3353US9984988B2Flip chip assembly with connected componentIBM·Filed 2017·Granted May 29, 2018·0 cites·16 claims
- 3452US7886435B2High performance chip carrier substrateIBM·Filed 2008·Granted Feb 15, 2011·0 cites·4 claims
- 3551US10806030B2Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performanceIBM·Filed 2015·Granted Oct 13, 2020·0 cites·13 claims
- 3647US10706204B2Automated generation of surface-mount package designIBM·Filed 2018·Granted Jul 7, 2020·0 cites·17 claims
- 3739US6461443B1Method and apparatus for continuous cleaning of substrate surfaces using ozoneIBM·Filed 2000·Granted Oct 8, 2002·3 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →