Inventor · disambiguated record
Jeff Jing Yuen Chan
Also filed as: CHAN JEFF · CHAN JEFF JING YUEN
6 granted patents·5 pending applications·7 citations·filing 2019–2024
73Inventor score
Files withARISTA NETWORKS INC11
Top patents by PatentIndex Score
11 records- 0187US11502767B2VLAN-aware clock synchronizationARISTA NETWORKS INC·Filed 2020·Granted Nov 15, 2022·3 cites·15 claims
- 0285US12250067B2Precision time protocol with multi-chassis link aggregation groupsARISTA NETWORKS INC·Filed 2022·Granted Mar 11, 2025·2 cites·19 claims
- 0380US11184097B2VLAN-aware clock hierarchyARISTA NETWORKS INC·Filed 2020·Granted Nov 23, 2021·2 cites·21 claims
- 0468US11870555B2VLAN-aware clock synchronizationARISTA NETWORKS INC·Filed 2022·Granted Jan 9, 2024·0 cites·20 claims
- 0552US11502766B2Precision time protocol with multi-chassis link aggregation groupsARISTA NETWORKS INC·Filed 2020·Granted Nov 15, 2022·0 cites·20 claims
- 0651US2025293918A1Optimized Traffic Switchover Across Redundant Switch CardsARISTA NETWORKS INC·Filed 2024·Application pending·0 cites
- 0748US2025055587A1Providing arbitrarily long timer from shorter underlying hardware counterARISTA NETWORKS INC·Filed 2023·Application pending·0 cites
- 0846US11070303B2Management message loop detection in precision time protocolARISTA NETWORKS INC·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 0946US2025158729A1PTP 1-Step Boundary Clock Without Hardware SynchronizationARISTA NETWORKS INC·Filed 2023·Application pending·0 cites
- 1046US2025080262A1System, apparatus, and method to manage multiple precision time protocol domainsARISTA NETWORKS INC·Filed 2024·Application pending·0 cites
- 1142US2023353489A1Systems and Methods for Managing Network SwitchesARISTA NETWORKS INC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →