Inventor · disambiguated record
Jeffrey R. Debord
Also filed as: DEBORD JEFFREY · DEBORD JEFFREY R · DEBORD JEFFREY ROBERT DOUGLAS
19 granted patents·1 pending application·57 citations·filing 1995–2018
92Inventor score
Top patents by PatentIndex Score
20 records- 0183US8552470B2Self-powered integrated circuit with multi-junction photovoltaic cellCHEN YUANNING·Filed 2011·Granted Oct 8, 2013·7 cites·3 claims
- 0282US9472571B2Isolated semiconductor layer over buried isolation layerTEXAS INSTRUMENTS INC·Filed 2014·Granted Oct 18, 2016·4 cites·2 claims
- 0381US9496313B2CMOS-based thermopile with reduced thermal conductanceTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 15, 2016·4 cites·5 claims
- 0481US5659034ALayered vanadium oxide compositionsNEC RESEARCH INST INC·Filed 1995·Granted Aug 19, 1997·22 cites·1 claims
- 0580US10032863B2Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formationTEXAS INSTRUMENTS INC·Filed 2016·Granted Jul 24, 2018·2 cites·15 claims
- 0680US9865498B2Isolated semiconductor layer over buried isolation layerTEXAS INSTRUMENTS INC·Filed 2016·Granted Jan 9, 2018·2 cites·12 claims
- 0775US9818795B2CMOS compatible thermopile with low impedance contactTEXAS INSTRUMENTS INC·Filed 2016·Granted Nov 14, 2017·2 cites·10 claims
- 0874US9330959B2Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formationTEXAS INSTRUMENTS INC·Filed 2014·Granted May 3, 2016·2 cites·15 claims
- 0970US9853086B2CMOS-based thermopile with reduced thermal conductanceTEXAS INSTRUMENTS INC·Filed 2016·Granted Dec 26, 2017·1 cites·14 claims
- 1070US9437652B2CMOS compatible thermopile with low impedance contactTEXAS INSTRUMENTS INC·Filed 2014·Granted Sep 6, 2016·2 cites·10 claims
- 1170US8883541B2Self-powered integrated circuit with multi-junction photovoltaic cellTEXAS INSTRUMENTS INC·Filed 2013·Granted Nov 11, 2014·2 cites·4 claims
- 1263US5717120ALayered vanadium oxide compositionsNEC RESEARCH INST INC·Filed 1996·Granted Feb 10, 1998·7 cites·3 claims
- 1360US10516019B2Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formationTEXAS INSTRUMENTS INC·Filed 2018·Granted Dec 24, 2019·0 cites·15 claims
- 1458US10886164B2Isolated semiconductor layer over buried isolation layerTEXAS INSTRUMENTS INC·Filed 2017·Granted Jan 5, 2021·0 cites·20 claims
- 1554US9231025B2CMOS-based thermoelectric device with reduced electrical resistanceTEXAS INSTRUMENTS INC·Filed 2014·Granted Jan 5, 2016·0 cites·5 claims
- 1653US9312164B2Localized region of isolated silicon over dielectric mesaTEXAS INSTRUMENTS INC·Filed 2014·Granted Apr 12, 2016·0 cites·22 claims
- 1748US9437799B2Method of forming a CMOS-based thermoelectric deviceTEXAS INSTRUMENTS INC·Filed 2015·Granted Sep 6, 2016·0 cites·15 claims
- 1847US2016225657A1Localized region of isolated silicon over dielectric mesaTEXAS INSTRUMENTS INC·Filed 2016·Application pending·0 cites
- 1945US9466520B2Localized region of isolated silicon over recessed dielectric layerTEXAS INSTRUMENTS INC·Filed 2014·Granted Oct 11, 2016·0 cites·20 claims
- 2033US5824813ALayered vanadium oxide compositionsNEC RESEARCH INST INC·Filed 1997·Granted Oct 20, 1998·0 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →