Inventor · disambiguated record
Jean Francois Deschenes
Also filed as: DESCHENES JEAN · DESCHENES JEAN FRANCOIS · DESCHENES JEAN-FRANÇOIS
6 granted patents·5 pending applications·6 citations·filing 2008–2024
69Inventor score
Top patents by PatentIndex Score
11 records- 0177US12423254B2Interrupt latency resilient UART driverSILICON LAB INC·Filed 2023·Granted Sep 23, 2025·1 cites·16 claims
- 0261US12443519B2Dynamic memory reservations for optimized and efficient RAM layoutSILICON LAB INC·Filed 2024·Granted Oct 14, 2025·0 cites·18 claims
- 0361US8275975B2Sequencer controlled system and method for controlling timing of operations of functional unitsORS ALI OSMAN·Filed 2008·Granted Sep 25, 2012·5 cites·18 claims
- 0458US12461584B2Optimal ram layout for power consumptionSILICON LAB INC·Filed 2024·Granted Nov 4, 2025·0 cites·18 claims
- 0547US2024289188A1Energy friendly event processing task modelSILICON LAB INC·Filed 2023·Application pending·0 cites
- 0645US2025335166A1Code Classification for Link-Time Code PlacementSILICON LAB INC·Filed 2024·Application pending·0 cites
- 0745US2025370920A1Linking RAM Code and Data with Multiple RAM AliasesSILICON LAB INC·Filed 2024·Application pending·0 cites
- 0842US2021141661A1Lightweight Context For CPU Idling Using A Real Time KernelSILICON LAB INC·Filed 2019·Application pending·0 cites
- 0936US2012085072A1Wrapping machineDESCHENES JEAN·Filed 2010·Application pending·0 cites
- 1035US10437659B2Built-in context error variablesSILICON LAB INC·Filed 2017·Granted Oct 8, 2019·0 cites·13 claims
- 1129US10318357B2Efficient locking mechanism for multiple operations rightsSILICON LAB INC·Filed 2017·Granted Jun 11, 2019·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →