Inventor · disambiguated record
Jeff P. Erhardt
Also filed as: ERHARDT JEFF · ERHARDT JEFF P
17 granted patents·692 citations·filing 1999–2005
96Inventor score
Top patents by PatentIndex Score
17 records- 0197US6835662B1Partially de-coupled core and periphery gate module processADVANCED MICRO DEVICES INC·Filed 2003·Granted Dec 28, 2004·180 cites·13 claims
- 0297US6513151B1Full flow focus exposure matrix analysis and electrical testing for new product mask evaluationADVANCED MICRO DEVICES INC·Filed 2001·Granted Jan 28, 2003·100 cites·27 claims
- 0396US7018868B1Disposable hard mask for memory bitline scalingADVANCED MICRO DEVICES INC·Filed 2004·Granted Mar 28, 2006·95 cites·19 claims
- 0488US6744105B1Memory array having shallow bit line with silicide contact portion and method of formationADVANCED MICRO DEVICES INC·Filed 2003·Granted Jun 1, 2004·47 cites·8 claims
- 0584US6963108B1Recessed channelADVANCED MICRO DEVICES INC·Filed 2003·Granted Nov 8, 2005·37 cites·35 claims
- 0684US6774432B1UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOLADVANCED MICRO DEVICES INC·Filed 2003·Granted Aug 10, 2004·31 cites·20 claims
- 0783US6514859B1Method of salicide formation with a double gate silicideADVANCED MICRO DEVICES INC·Filed 2000·Granted Feb 4, 2003·33 cites·24 claims
- 0881US6576548B1Method of manufacturing a semiconductor device with reliable contacts/viasADVANCED MICRO DEVICES INC·Filed 2002·Granted Jun 10, 2003·28 cites·20 claims
- 0977US6855608B1Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistanceADVANCED MICRO DEVICES INC·Filed 2003·Granted Feb 15, 2005·17 cites·24 claims
- 1074US6399467B1Method of salicide formationADVANCED MICRO DEVICES INC·Filed 2000·Granted Jun 4, 2002·19 cites·16 claims
- 1173US6987048B1Memory device having silicided bitlines and method of forming the sameADVANCED MICRO DEVICES INC·Filed 2003·Granted Jan 17, 2006·29 cites·5 claims
- 1272US6613500B1Reducing resist residue defects in open area on patterned wafer using trim maskADVANCED MICRO DEVICES INC·Filed 2001·Granted Sep 2, 2003·11 cites·22 claims
- 1369US7118967B1Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processingSPANSION LLC·Filed 2003·Granted Oct 10, 2006·15 cites·20 claims
- 1467US7476604B1Aggressive cleaning process for semiconductor device contact formationADVANCED MICRO DEVICES INC·Filed 2005·Granted Jan 13, 2009·3 cites·8 claims
- 1565US6387786B1Method of salicide formation by siliciding a gate area prior to siliciding a source and drain areaADVANCED MICRO DEVICES INC·Filed 2000·Granted May 14, 2002·12 cites·32 claims
- 1663US7018896B2UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processingADVANCED MICRO DEVICES INC·Filed 2004·Granted Mar 28, 2006·9 cites·20 claims
- 1759US6521501B1Method of forming a CMOS transistor having ultra shallow source and drain regionsADVANCED MICRO DEVICES INC·Filed 1999·Granted Feb 18, 2003·26 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →