Inventor · disambiguated record
Jerry D. Hayes
Also filed as: HAYES JERRY D · HAYES JERRY DEAN
33 granted patents·3 pending applications·545 citations·filing 1997–2012
97Inventor score
Top patents by PatentIndex Score
36 records- 0198US6983432B2Circuit and method for modeling I/OIBM·Filed 2002·Granted Jan 3, 2006·204 cites·28 claims
- 0295US8229683B2Test circuit for bias temperature instability recovery measurementsGEBARA FADI H·Filed 2010·Granted Jul 24, 2012·14 cites·8 claims
- 0393US7397259B1Method and apparatus for statistical CMOS device characterizationIBM·Filed 2007·Granted Jul 8, 2008·21 cites·6 claims
- 0492US7089143B2Method and system for evaluating timing in an integrated circuitIBM·Filed 2004·Granted Aug 8, 2006·41 cites·19 claims
- 0589US7949482B2Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recoveryIBM·Filed 2008·Granted May 24, 2011·13 cites·15 claims
- 0689US7444608B2Method and system for evaluating timing in an integrated circuitIBM·Filed 2006·Granted Oct 28, 2008·13 cites·11 claims
- 0787US7818137B2Characterization circuit for fast determination of device capacitance variationIBM·Filed 2009·Granted Oct 19, 2010·12 cites·18 claims
- 0886US7716616B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2007·Granted May 11, 2010·12 cites·25 claims
- 0985US7418689B2Method of generating wiring routes with matching delay in the presence of process variationIBM·Filed 2005·Granted Aug 26, 2008·12 cites·18 claims
- 1084US8676516B2Test circuit for bias temperature instability recovery measurementsGEBARA FADI H·Filed 2012·Granted Mar 18, 2014·4 cites·7 claims
- 1184US8154309B2Configurable PSRO structure for measuring frequency dependent capacitive loadsAGARWAL KANAK B·Filed 2009·Granted Apr 10, 2012·12 cites·14 claims
- 1284US7302673B2Method and system for performing shapes correction of a multi-cell reticle photomask designIBM·Filed 2005·Granted Nov 27, 2007·7 cites·20 claims
- 1382US8120356B2Measurement methodology and array structure for statistical stress and test of reliabilty structuresAGARWAL KANAK B·Filed 2009·Granted Feb 21, 2012·11 cites·25 claims
- 1482US6487701B1System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technologyIBM·Filed 2000·Granted Nov 26, 2002·27 cites·39 claims
- 1581US7401307B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2004·Granted Jul 15, 2008·24 cites·9 claims
- 1679US7834649B2Method and apparatus for statistical CMOS device characterizationIBM·Filed 2010·Granted Nov 16, 2010·3 cites·3 claims
- 1777US7266474B2Ring oscillator structure and method of separating random and systematic tolerance valuesIBM·Filed 2005·Granted Sep 4, 2007·8 cites·10 claims
- 1876US7174523B2Variable sigma adjust methodology for static timingIBM·Filed 2004·Granted Feb 6, 2007·21 cites·7 claims
- 1975US7870525B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2008·Granted Jan 11, 2011·5 cites·20 claims
- 2075US7865861B2Method of generating wiring routes with matching delay in the presence of process variationIBM·Filed 2008·Granted Jan 4, 2011·5 cites·13 claims
- 2173US7823115B2Method of generating wiring routes with matching delay in the presence of process variationIBM·Filed 2008·Granted Oct 26, 2010·4 cites·2 claims
- 2272US8217671B2Parallel array architecture for constant current electro-migration stress testingAGARWAL KANAK B·Filed 2009·Granted Jul 10, 2012·6 cites·19 claims
- 2372US7868640B2Array-based early threshold voltage recovery characterization measurementIBM·Filed 2008·Granted Jan 11, 2011·6 cites·20 claims
- 2471US7962874B2Method and system for evaluating timing in an integrated circuitIBM·Filed 2008·Granted Jun 14, 2011·4 cites·2 claims
- 2571US7280939B2System and method of analyzing timing effects of spatial distribution in circuitsIBM·Filed 2004·Granted Oct 9, 2007·13 cites·4 claims
- 2657US7768814B2Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environmentIBM·Filed 2008·Granted Aug 3, 2010·5 cites·20 claims
- 2756US6090152AMethod and system for using voltage and temperature adders to account for variations in operating conditions during timing simulationIBM·Filed 1997·Granted Jul 18, 2000·36 cites·20 claims
- 2852US7680626B2System and method of analyzing timing effects of spatial distribution in circuitsIBM·Filed 2007·Granted Mar 16, 2010·0 cites·31 claims
- 2950US8336008B2Characterization of long range variabilityCULP JAMES A·Filed 2009·Granted Dec 18, 2012·0 cites·23 claims
- 3050US7231335B2Method and apparatus for performing input/output floor planning on an integrated circuit designIBM·Filed 2003·Granted Jun 12, 2007·2 cites·8 claims
- 3147US7782076B2Method and apparatus for statistical CMOS device characterizationIBM·Filed 2008·Granted Aug 24, 2010·0 cites·9 claims
- 3247US2007089078A1Variable Sigma Adjust Methodology For Static TimingENGEL JAMES J·Filed 2006·Application pending·0 cites
- 3347US2009164155A1Method and system for isolating dopant fluctuation and device length variation from statistical measurements of threshold voltageAGARWAL KANAK B·Filed 2007·Application pending·0 cites
- 3446US8862426B2Method and test system for fast determination of parameter variation statisticsAGARWAL KANAK B·Filed 2007·Granted Oct 14, 2014·0 cites·3 claims
- 3544US8089296B2On-chip measurement of signalsAGARWAL KANAK BEHARI·Filed 2009·Granted Jan 3, 2012·0 cites·20 claims
- 3639US2008126061A1Analysis techniques to reduce simulations to characterize the effect of variations in transistor circuitsHAYES JERRY D·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →