Inventor · disambiguated record
Jen-Shou Hsu
Also filed as: HSU JEN-SHOU
22 granted patents·137 citations·filing 2004–2022
94Inventor score
Files withETRON TECHNOLOGY INC11ELITE SEMICONDUCTOR MEMORY TECH INC4ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC4HSU JEN-SHOU2ELITE SEMICONDUCTOR ESMT1
Top patents by PatentIndex Score
22 records- 0194US11100963B1Data first-in first-out (FIFO) circuitELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC·Filed 2020·Granted Aug 24, 2021·5 cites·15 claims
- 0294US10916293B1Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuitELITE SEMICONDUCTOR MEMORY TECH INC·Filed 2020·Granted Feb 9, 2021·10 cites·13 claims
- 0386US7292494B2Internal power management scheme for a memory chip in deep power down modeETRON TECHNOLOGY INC·Filed 2006·Granted Nov 6, 2007·15 cites·13 claims
- 0485US7741898B2Charge pump circuit for high voltage generationETRON TECHNOLOGY INC·Filed 2007·Granted Jun 22, 2010·24 cites·50 claims
- 0583US8289795B1Semiconductor memory device and method of testing the sameHSU JEN-SHOU·Filed 2011·Granted Oct 16, 2012·11 cites·12 claims
- 0682US7570104B2Charge pump circuit control systemETRON TECHNOLOGY INC·Filed 2007·Granted Aug 4, 2009·18 cites·18 claims
- 0780US7277315B2Multiple power supplies for the driving circuit of local word line driver of DRAMETRON TECHNOLOGY INC·Filed 2005·Granted Oct 2, 2007·15 cites·12 claims
- 0879US11545200B1Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory deviceELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC·Filed 2021·Granted Jan 3, 2023·1 cites·12 claims
- 0978US7551018B2Decoupling capacitor circuitETRON TECHNOLOGY INC·Filed 2007·Granted Jun 23, 2009·8 cites·18 claims
- 1065US9484117B2Semiconductor memory device having compression test modeELITE SEMICONDUCTOR MEMORY TECH INC·Filed 2013·Granted Nov 1, 2016·3 cites·20 claims
- 1164US8384459B2Delay line circuit and phase interpolation module thereofELITE SEMICONDUCTOR ESMT·Filed 2011·Granted Feb 26, 2013·2 cites·15 claims
- 1264US7623388B2Method for detecting erroneous word lines of a memory array and device thereofETRON TECHNOLOGY INC·Filed 2008·Granted Nov 24, 2009·7 cites·12 claims
- 1360US7434985B2Calibrated built-in temperature sensor and calibration method thereofETRON TECHNOLOGY INC·Filed 2005·Granted Oct 14, 2008·4 cites·14 claims
- 1454US11955163B2Method and circuit for adaptive column-select line signal generationELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC·Filed 2022·Granted Apr 9, 2024·0 cites·11 claims
- 1554US7817485B2Memory testing system and memory module thereofETRON TECHNOLOGY INC·Filed 2008·Granted Oct 19, 2010·4 cites·20 claims
- 1654US7002870B2Speeding up the power-up procedure for low power RAMETRON TECHNOLOGY INC·Filed 2004·Granted Feb 21, 2006·8 cites·25 claims
- 1748US7479775B2Negative voltage generatorETRON TECHNOLOGY INC·Filed 2006·Granted Jan 20, 2009·2 cites·24 claims
- 1847US9575114B2Test system and deviceELITE SEMICONDUCTOR MEMORY TECH INC·Filed 2014·Granted Feb 21, 2017·0 cites·12 claims
- 1945US11073862B2Synchronization circuit and cascaded synchronization circuit for converting asynchronous signal into synchronous signalELITE SEMICONDUCTOR MEMORY TECH INC·Filed 2019·Granted Jul 27, 2021·0 cites·15 claims
- 2042US11727968B2Method for self-calibrating tDQSCK that is skew between rising edge of memory clock signal and rising edge of DQS signal during read operation and associated signal processing circuitELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC·Filed 2021·Granted Aug 15, 2023·0 cites·15 claims
- 2138US7796448B2Trigger circuit of a column redundant circuit and related column redundant deviceETRON TECHNOLOGY INC·Filed 2008·Granted Sep 14, 2010·0 cites·20 claims
- 2231US8472265B2Repairing circuit for memory circuit and method thereof and memory circuit using the sameHSU JEN-SHOU·Filed 2011·Granted Jun 25, 2013·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →