Inventor · disambiguated record
Jens Leenstra
Also filed as: LEENSTRA JENS
33 granted patents·2 pending applications·225 citations·filing 2001–2015
96Inventor score
Top patents by PatentIndex Score
35 records- 0193US8046566B2Method to reduce power consumption of a register file with multi SMT supportIBM·Filed 2008·Granted Oct 25, 2011·39 cites·13 claims
- 0292US9207995B2Mechanism to speed-up multithreaded execution by register file write port reallocationBOERSMA MAARTEN J·Filed 2011·Granted Dec 8, 2015·26 cites·12 claims
- 0384US7509511B1Reducing register file leakage current within a processorIBM·Filed 2008·Granted Mar 24, 2009·14 cites·1 claims
- 0483US6785781B2Read/write alignment scheme for port reduction of multi-port SRAM cellsIBM·Filed 2001·Granted Aug 31, 2004·36 cites·13 claims
- 0582US7890901B2Method and system for verifying the equivalence of digital circuitsIBM·Filed 2007·Granted Feb 15, 2011·12 cites·15 claims
- 0678US7783690B2Electronic circuit for implementing a permutation operationIBM·Filed 2006·Granted Aug 24, 2010·12 cites·15 claims
- 0778US7769986B2Method and apparatus for register renamingIBM·Filed 2007·Granted Aug 3, 2010·8 cites·16 claims
- 0876US8949575B2Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latencyBOERSMA MAARTEN J·Filed 2011·Granted Feb 3, 2015·4 cites·10 claims
- 0975US7228403B2Method for handling 32 bit results for an out-of-order processor with a 64 bit architectureIBM·Filed 2001·Granted Jun 5, 2007·23 cites·10 claims
- 1074US8903882B2Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program productBOERSMA MAARTEN J·Filed 2011·Granted Dec 2, 2014·4 cites·13 claims
- 1172US8843527B2Fast predicate table scans using single instruction, multiple data architectureIBM·Filed 2013·Granted Sep 23, 2014·3 cites·9 claims
- 1271US9164725B2Apparatus and method for calculating an SHA-2 hash function in a general purpose processorBOERSMA MAARTEN J·Filed 2011·Granted Oct 20, 2015·3 cites·20 claims
- 1367US6725332B2Hierarchical priority filter with integrated serialization for determining the entry with the highest priority in a buffer memoryIBM·Filed 2001·Granted Apr 20, 2004·13 cites·15 claims
- 1466US8972961B2Instruction scheduling approach to improve processor performanceKOEHL JUERGEN·Filed 2011·Granted Mar 3, 2015·2 cites·11 claims
- 1566US8935685B2Instruction scheduling approach to improve processor performanceKOEHL JUERGEN·Filed 2012·Granted Jan 13, 2015·2 cites·3 claims
- 1663US7844799B2Method and system for pipeline reductionIBM·Filed 2001·Granted Nov 30, 2010·10 cites·16 claims
- 1760US8312069B2Permute unit and method to operate a permute unitGEMMEKE TOBIAS·Filed 2007·Granted Nov 13, 2012·2 cites·9 claims
- 1856US6829699B2Rename finish conflict detection and recoveryIBM·Filed 2001·Granted Dec 7, 2004·4 cites·9 claims
- 1955US8959276B2Byte selection and steering logic for combined byte shift and byte permute vector unitIBM·Filed 2014·Granted Feb 17, 2015·0 cites·7 claims
- 2054US8977835B2Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latencyIBM·Filed 2013·Granted Mar 10, 2015·0 cites·5 claims
- 2153US6918119B2Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environmentsIBM·Filed 2001·Granted Jul 12, 2005·3 cites·16 claims
- 2251US8959275B2Byte selection and steering logic for combined byte shift and byte permute vector unitIBM·Filed 2012·Granted Feb 17, 2015·0 cites·7 claims
- 2351US7735038B2Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuitIBM·Filed 2007·Granted Jun 8, 2010·1 cites·7 claims
- 2451US7639046B2Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuitIBM·Filed 2007·Granted Dec 29, 2009·1 cites·12 claims
- 2550US9256430B2Instruction scheduling approach to improve processor performanceIBM·Filed 2015·Granted Feb 9, 2016·0 cites·14 claims
- 2650US7913132B2System and method for scanning sequential logic elementsIBM·Filed 2008·Granted Mar 22, 2011·1 cites·14 claims
- 2746US7962538B2Method of operand width reduction to enable usage of narrower saturation adderIBM·Filed 2006·Granted Jun 14, 2011·0 cites·15 claims
- 2844US2007165343A1Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a CircuitBAROWSKI HARRY·Filed 2006·Application pending·0 cites
- 2943US7469332B2Systems and methods for adaptively mapping an instruction cacheIBM·Filed 2005·Granted Dec 23, 2008·0 cites·14 claims
- 3042US8832158B2Fast predicate table scans using single instruction, multiple data architectureDINER EDUARD·Filed 2012·Granted Sep 9, 2014·0 cites·13 claims
- 3140US2002152259A1Pre-committing instruction sequencesIBM·Filed 2002·Application pending·0 cites
- 3239US6873567B2Device and method for decoding an address word into word-line signalsIBM·Filed 2003·Granted Mar 29, 2005·2 cites·9 claims
- 3338US6977863B2Device and method for decoding an address word into word-line signalsIBM·Filed 2005·Granted Dec 20, 2005·0 cites·5 claims
- 3434US6518793B2Embedding of dynamic circuits in a static environmentIBM·Filed 2001·Granted Feb 11, 2003·0 cites·19 claims
- 3531US9043673B2Techniques for reusing components of a logical operations functional block as an error correction code correction unitIBM·Filed 2013·Granted May 26, 2015·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →