Inventor · disambiguated record
Jerry Don Lewis
Also filed as: LEWIS JERRY D · LEWIS JERRY DON
153 granted patents·4 pending applications·3,950 citations·filing 1994–2008
99Inventor score
Top patents by PatentIndex Score
157 records- 0190US8077602B2Performing dynamic request routing based on broadcast queue depthsARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Dec 13, 2011·23 cites·21 claims
- 0287US7779148B2Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chipsIBM·Filed 2008·Granted Aug 17, 2010·15 cites·18 claims
- 0386US5895495ADemand-based larx-reserve protocol for SMP system busesIBM·Filed 1997·Granted Apr 20, 1999·121 cites·20 claims
- 0484US7308558B2Multiprocessor data processing system having scalable data interconnect and data routing mechanismIBM·Filed 2004·Granted Dec 11, 2007·39 cites·17 claims
- 0584US5613153ACoherency and synchronization mechanisms for I/O channel controllers in a data processing systemIBM·Filed 1994·Granted Mar 18, 1997·96 cites·13 claims
- 0683US7958309B2Dynamic selection of a memory access sizeIBM·Filed 2008·Granted Jun 7, 2011·12 cites·15 claims
- 0782US6801984B2Imprecise snooping based invalidation mechanismIBM·Filed 2001·Granted Oct 5, 2004·34 cites·26 claims
- 0880US6848003B1Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined responseIBM·Filed 1999·Granted Jan 25, 2005·87 cites·20 claims
- 0980US6591321B1Multiprocessor system bus protocol with group addresses, responses, and prioritiesIBM·Filed 1999·Granted Jul 8, 2003·89 cites·24 claims
- 1079US8108619B2Cache management for partial cache line operationsARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Jan 31, 2012·9 cites·15 claims
- 1179US6587924B2Scarfing within a hierarchical memory architectureIBM·Filed 2001·Granted Jul 1, 2003·27 cites·17 claims
- 1277US6192458B1High performance cache directory addressing scheme for variable cache sizes utilizing associativityIBM·Filed 1998·Granted Feb 20, 2001·78 cites·22 claims
- 1377US6018791AApparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read statesIBM·Filed 1998·Granted Jan 25, 2000·78 cites·6 claims
- 1477US5974507AOptimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithmIBM·Filed 1997·Granted Oct 26, 1999·76 cites·17 claims
- 1576US8024527B2Partial cache line accesses based on memory access patternsIBM·Filed 2008·Granted Sep 20, 2011·7 cites·20 claims
- 1676US6006311ADynamic updating of repair mask used for cache defect avoidanceIBM·Filed 1997·Granted Dec 21, 1999·74 cites·14 claims
- 1775US6058456ASoftware-managed programmable unified/split caching mechanism for instructions and dataIBM·Filed 1997·Granted May 2, 2000·70 cites·10 claims
- 1874US6910062B2Method and apparatus for transmitting packets within a symmetric multiprocessor systemIBM·Filed 2001·Granted Jun 21, 2005·19 cites·8 claims
- 1974US6865695B2Robust system bus recoveryIBM·Filed 2001·Granted Mar 8, 2005·20 cites·25 claims
- 2074US6587926B2Incremental tag build for hierarchical memory architectureIBM·Filed 2001·Granted Jul 1, 2003·19 cites·12 claims
- 2174US6212605B1Eviction override for larx-reserved addressesIBM·Filed 1997·Granted Apr 3, 2001·67 cites·15 claims
- 2273US7213169B2Method and apparatus for performing imprecise bus tracing in a data processing system having a distributed memoryIBM·Filed 2003·Granted May 1, 2007·20 cites·5 claims
- 2373US6192451B1Cache coherency protocol for a data processing system including a multi-level memory hierarchyIBM·Filed 1998·Granted Feb 20, 2001·67 cites·16 claims
- 2472US6330643B1Cache coherency protocols with global and local posted operationsIBM·Filed 1998·Granted Dec 11, 2001·64 cites·18 claims
- 2572US6021468ACache coherency protocol with efficient write-through aliasingIBM·Filed 1997·Granted Feb 1, 2000·53 cites·20 claims
- 2671US6138218AForward progress on retried snoop hits by altering the coherency state of a local cacheIBM·Filed 1998·Granted Oct 24, 2000·57 cites·28 claims
- 2771US5958068ACache array defect functional bypassing using repair maskIBM·Filed 1997·Granted Sep 28, 1999·58 cites·8 claims
- 2869US7827428B2System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Nov 2, 2010·4 cites·25 claims
- 2969US6480975B1ECC mechanism for set associative cache arrayIBM·Filed 1998·Granted Nov 12, 2002·53 cites·21 claims
- 3068US6343347B1Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transactionIBM·Filed 1999·Granted Jan 29, 2002·49 cites·21 claims
- 3168US6029204APrecise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retriesIBM·Filed 1997·Granted Feb 22, 2000·53 cites·6 claims
- 3267US6502171B1Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf dataIBM·Filed 1999·Granted Dec 31, 2002·48 cites·17 claims
- 3367US6353875B1Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactionsIBM·Filed 1999·Granted Mar 5, 2002·47 cites·22 claims
- 3467US6275909B1Multiprocessor system bus with system controller explicitly updating snooper cache state informationIBM·Filed 1999·Granted Aug 14, 2001·48 cites·20 claims
- 3566US8117401B2Interconnect operation indicating acceptability of partial data deliveryARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Feb 14, 2012·3 cites·11 claims
- 3665US6343344B1System bus directory snooping mechanism for read/castout (RCO) address transactionIBM·Filed 1999·Granted Jan 29, 2002·43 cites·17 claims
- 3765US5963974ACache intervention from a cache line exclusively holding an unmodified valueIBM·Filed 1997·Granted Oct 5, 1999·46 cites·18 claims
- 3865US5896539AMethod and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random prioritiesIBM·Filed 1997·Granted Apr 20, 1999·45 cites·25 claims
- 3964US6195729B1Deallocation with cache update protocol (L2 evictions)IBM·Filed 1998·Granted Feb 27, 2001·43 cites·14 claims
- 4064US5978888AHardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levelsIBM·Filed 1997·Granted Nov 2, 1999·42 cites·15 claims
- 4163US5940856ACache intervention from only one of many cache lines sharing an unmodified valueIBM·Filed 1997·Granted Aug 17, 1999·41 cites·18 claims
- 4262US8255635B2Claiming coherency ownership of a partial cache line of dataARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Aug 28, 2012·2 cites·14 claims
- 4362US7302616B2Method and apparatus for performing bus tracing with scalable bandwidth in a data processing system having a distributed memoryIBM·Filed 2003·Granted Nov 27, 2007·9 cites·6 claims
- 4462US6470442B1Processor assigning data to hardware partition based on selectable hash of data addressIBM·Filed 1999·Granted Oct 22, 2002·37 cites·20 claims
- 4562US6415424B1Multiprocessor system with a high performance integrated distributed switch (IDS) controllerIBM·Filed 1999·Granted Jul 2, 2002·38 cites·10 claims
- 4662US6175930B1Demand based sync bus operationIBM·Filed 1998·Granted Jan 16, 2001·39 cites·19 claims
- 4762US6141733ACache coherency protocol with independent implementation of optimized cache operationsIBM·Filed 1998·Granted Oct 31, 2000·39 cites·22 claims
- 4861US6553442B1Bus master for SMP execution of global operations utilizing a single token with implied releaseIBM·Filed 1999·Granted Apr 22, 2003·36 cites·22 claims
- 4961US6157980ACache directory addressing scheme for variable cache sizesIBM·Filed 1998·Granted Dec 5, 2000·37 cites·19 claims
- 5061US6145059ACache coherency protocols with posted operations and tagged coherency statesIBM·Filed 1998·Granted Nov 7, 2000·38 cites·16 claims
Showing the top 50 of 157 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Jerry Don Lewis files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →