Inventor · disambiguated record
Jeffrey A. Lohman
Also filed as: LOHMAN JEFFREY · LOHMAN JEFFREY A
20 granted patents·606 citations·filing 1990–2020
96Inventor score
Top patents by PatentIndex Score
20 records- 0193US5430884AScalar/vector processorCRAY RESEARCH INC·Filed 1990·Granted Jul 4, 1995·131 cites·11 claims
- 0290US11360780B2Instruction-level context switch in SIMD processorAPPLE INC·Filed 2020·Granted Jun 14, 2022·3 cites·20 claims
- 0390US7113969B1Formatting denormal numbers for processing in a pipelined floating point unitNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 26, 2006·59 cites·20 claims
- 0484US6523050B1Integer to floating point conversion using one's complement with subsequent correction to eliminate two's complement in critical pathNAT SEMICONDUCTOR CORP·Filed 1999·Granted Feb 18, 2003·59 cites·20 claims
- 0580US11204774B1Thread-group-scoped gate instructionAPPLE INC·Filed 2020·Granted Dec 21, 2021·1 cites·20 claims
- 0680US6801924B1Formatting denormal numbers for processing in a pipelined floating point unitNAT SEMICONDUCTOR CORP·Filed 1999·Granted Oct 5, 2004·81 cites·21 claims
- 0773US5640524AMethod and apparatus for chaining vector instructionsCRAY RESEARCH INC·Filed 1995·Granted Jun 17, 1997·41 cites·8 claims
- 0870US5745721APartitioned addressing apparatus for vector/scalar registersCRAY RESEARCH INC·Filed 1995·Granted Apr 28, 1998·34 cites·2 claims
- 0969US6907518B1Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the sameNAT SEMICONDUCTOR CORP·Filed 2003·Granted Jun 14, 2005·13 cites·20 claims
- 1068US6714957B1System and method for efficient processing of denormal results as hardware exceptionsNAT SEMICONDUCTOR CORP·Filed 2000·Granted Mar 30, 2004·14 cites·20 claims
- 1167US6629231B1System and method for efficient register file conversion of denormal numbers between scalar and SIMD formatsNAT SEMICONDUCTOR CORP·Filed 2000·Granted Sep 30, 2003·12 cites·33 claims
- 1265US5659706AVector/scalar processor with simultaneous processing and instruction cache fillingCRAY RESEARCH INC·Filed 1995·Granted Aug 19, 1997·28 cites·1 claims
- 1360US6757812B1Leading bit prediction with in-parallel correctionNAT SEMICONDUCTOR CORP·Filed 2002·Granted Jun 29, 2004·6 cites·24 claims
- 1456US5544337AVector processor having registers for control by vector resistersCRAY RESEARCH INC·Filed 1995·Granted Aug 6, 1996·33 cites·7 claims
- 1553US5623650AMethod of processing a sequence of conditional vector IF statementsCRAY RESEARCH INC·Filed 1995·Granted Apr 22, 1997·28 cites·4 claims
- 1652US5706490AMethod of processing conditional branch instructions in scalar/vector processorCRAY RESEARCH INC·Filed 1995·Granted Jan 6, 1998·15 cites·2 claims
- 1744US6405232B1Leading bit prediction with in-parallel correctionNAT SEMICONDUCTOR CORP·Filed 1999·Granted Jun 11, 2002·14 cites·20 claims
- 1843US6581155B1Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the sameNAT SEMICONDUCTOR CORP·Filed 1999·Granted Jun 17, 2003·14 cites·20 claims
- 1941US5598547AVector processor having functional unit paths of differing pipeline lengthsCRAY RESEARCH INC·Filed 1995·Granted Jan 28, 1997·14 cites·2 claims
- 2039US5717881AData processing system for processing one and two parcel instructionsCRAY RESEARCH INC·Filed 1995·Granted Feb 10, 1998·6 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →