Inventor · disambiguated record
Jeffery Thomas Nichols
Also filed as: NICHOLS JEFFERY T · NICHOLS JEFFERY THOMAS
18 granted patents·1 pending application·261 citations·filing 2003–2024
95Inventor score
Top patents by PatentIndex Score
19 records- 0197US11184112B1OpenFEC error markingCIENA CORP·Filed 2021·Granted Nov 23, 2021·5 cites·20 claims
- 0293US10063336B1Protected transponded services integrated with control plane switched servicesCIENA CORP·Filed 2017·Granted Aug 28, 2018·14 cites·20 claims
- 0392US9980021B2Scalable switch fabric using optical interconnectsCIENA CORP·Filed 2016·Granted May 22, 2018·12 cites·14 claims
- 0492US8356233B2Pseudo-noise insertion on unacceptable input data sequence in optical networksCIENA CORP·Filed 2010·Granted Jan 15, 2013·12 cites·16 claims
- 0590US8306420B2Optical network real time latency measurement systems and methodsCONKLIN RICHARD W·Filed 2010·Granted Nov 6, 2012·14 cites·19 claims
- 0690US7073117B1Method and apparatus for generating bit errors in a forward error correction (FEC) system to estimate power dissipation characteristics of the systemCIENA CORP·Filed 2003·Granted Jul 4, 2006·48 cites·25 claims
- 0789US8830993B1Extensible time space switch systems and methods for high capacity multi-service applicationsDUBLIN IAN·Filed 2011·Granted Sep 9, 2014·28 cites·11 claims
- 0888US11552722B2Precision time protocol using a coherent optical DSP frameCIENA CORP·Filed 2020·Granted Jan 10, 2023·2 cites·18 claims
- 0986US12149352B2OpenFEC error markingCIENA CORP·Filed 2021·Granted Nov 19, 2024·1 cites·20 claims
- 1082US9538264B2ODUflex resizing systems and methodsSUREK STEVEN ARVO·Filed 2014·Granted Jan 3, 2017·7 cites·11 claims
- 1182US7039854B1Method and apparatus for performing syndrome computation in a decoder of a forward error correction (FEC) systemCIENA CORP·Filed 2003·Granted May 2, 2006·30 cites·20 claims
- 1278US8732358B2Circuit systems and methods using prime number interleave optimization for byte lane to time slice conversionCIENA CORP·Filed 2012·Granted May 20, 2014·5 cites·20 claims
- 1376US7058876B1Method and apparatus for use in a decoder of a forward error correction (FEC) system for locating bit errors in a error locator polynomialCIENA CORP·Filed 2003·Granted Jun 6, 2006·23 cites·20 claims
- 1476US2025038888A1OpenFEC error markingCIENA CORP·Filed 2024·Application pending·0 cites
- 1575US7096408B1Method and apparatus for computing the error locator polynomial in a decoder of a forward error correction (FEC) systemCIENA CORP·Filed 2003·Granted Aug 22, 2006·21 cites·18 claims
- 1674US7003708B1Method and apparatus for generating bit errors with a poisson error distributionCIENA CORP·Filed 2003·Granted Feb 21, 2006·10 cites·18 claims
- 1772US8458560B2Systems and methods for efficient parallel implementation of burst error correction codesNICHOLS JEFFERY T·Filed 2008·Granted Jun 4, 2013·10 cites·18 claims
- 1867US9825883B2Extensible time space switch systems and methodsNICHOLS JEFFERY THOMAS·Filed 2010·Granted Nov 21, 2017·5 cites·12 claims
- 1966US6986097B1Method and apparatus for generating parity bits in a forward error correction (FEC) systemCIENA CORP·Filed 2003·Granted Jan 10, 2006·14 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →