Inventor · disambiguated record
Jens Polney
Also filed as: POLNEY JENS
10 granted patents·4 pending applications·62 citations·filing 2001–2025
85Inventor score
Top patents by PatentIndex Score
14 records- 0194US9818462B1Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory deviceMICRON TECHNOLOGY INC·Filed 2017·Granted Nov 14, 2017·23 cites·9 claims
- 0280US6363017B2Method and apparatus for alternate operation of a random access memory in single-memory operating mode and in combined multi-memory operating modeINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 26, 2002·32 cites·6 claims
- 0370US10297298B2Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory deviceMICRON TECHNOLOGY INC·Filed 2017·Granted May 21, 2019·2 cites·12 claims
- 0463US10943627B2Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory deviceMICRON TECHNOLOGY INC·Filed 2019·Granted Mar 9, 2021·1 cites·16 claims
- 0557US7554875B2Bus structure, memory chip and integrated circuitQIMONDA AG·Filed 2007·Granted Jun 30, 2009·1 cites·23 claims
- 0655US2025299767A1Operational modes of a memory registerMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 0754US2025013258A1Systems and techniques for clock doublingMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 0852US2023215828A1Layouts of data pads on a semiconductor dieMICRON TECHNOLOGY INC·Filed 2022·Application pending·0 cites
- 0944US6504359B2Method and device for testing electronic componentsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Jan 7, 2003·3 cites·24 claims
- 1036US7573760B2Integrated circuit for sampling a sequence of data packets at a data outputQIMONDA AG·Filed 2007·Granted Aug 11, 2009·0 cites·24 claims
- 1134US7123523B2Integrated circuit having an input circuitINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 17, 2006·0 cites·10 claims
- 1232US6977862B2Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuitINFINEON TECHNOLOGIES AG·Filed 2004·Granted Dec 20, 2005·0 cites·20 claims
- 1331US2006133172A1Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memorySCHNABEL FLORIAN·Filed 2005·Application pending·0 cites
- 1429US6525597B2Circuit configuration with internal supply voltageINFINEON TECHNOLOGIES AG·Filed 2001·Granted Feb 25, 2003·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →