Inventor · disambiguated record
Jeff Rearick
Also filed as: REARICK JEFF
16 granted patents·3 pending applications·516 citations·filing 1997–2003
95Inventor score
Top patents by PatentIndex Score
19 records- 0194US6715105B1Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access portAGILENT TECHNOLOGIES INC·Filed 2000·Granted Mar 30, 2004·98 cites·17 claims
- 0292US6708139B2Method and apparatus for measuring the quality of delay test patternsAGILENT TECHNOLOGIES INC·Filed 2002·Granted Mar 16, 2004·56 cites·37 claims
- 0387US6707313B1Systems and methods for testing integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2003·Granted Mar 16, 2004·34 cites·20 claims
- 0486US6653957B1SERDES cooperates with the boundary scan test techniqueAGILENT TECHNOLOGIES INC·Filed 2002·Granted Nov 25, 2003·67 cites·9 claims
- 0585US6865706B1Apparatus and method for generating a set of test vectors using nonrandom fillingAGILENT TECHNOLOGIES INC·Filed 2000·Granted Mar 8, 2005·32 cites·22 claims
- 0685US6380780B1Integrated circuit with scan flip-flopAGILENT TECHNOLOGIES INC·Filed 2000·Granted Apr 30, 2002·33 cites·19 claims
- 0785US5905986AHighly compressible representation of test pattern dataHEWLETT PACKARD CO·Filed 1997·Granted May 18, 1999·60 cites·12 claims
- 0879US7039845B2Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faultsREARICK JEFF·Filed 2002·Granted May 2, 2006·27 cites·17 claims
- 0978US7139955B2Hierarchically-controlled automatic test pattern generationAVAGO TECHNOLOGIES GENERAL IP·Filed 2002·Granted Nov 21, 2006·25 cites·27 claims
- 1078US6721920B2Systems and methods for facilitating testing of pad drivers of integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2001·Granted Apr 13, 2004·28 cites·10 claims
- 1177US6396312B1Gate transition counterAGILENT TECHNOLOGIES INC·Filed 2000·Granted May 28, 2002·21 cites·33 claims
- 1261US6763486B2Method and apparatus of boundary scan testing for AC-coupled differential data pathsAGILENT TECHNOLOGIES INC·Filed 2001·Granted Jul 13, 2004·9 cites·19 claims
- 1356US6239607B1Simulation-based method for estimating leakage currents in defect-free integrated circuitsAGILENT TECHNOLOGIES INC·Filed 1998·Granted May 29, 2001·20 cites·8 claims
- 1452US6944837B2System and method for evaluating an integrated circuit designAGILENT TECHNOLOGIES INC·Filed 2002·Granted Sep 13, 2005·3 cites·28 claims
- 1549US6895562B2Partitioning integrated circuit hierarchyAGILENT TECHNOLOGIES INC·Filed 2002·Granted May 17, 2005·2 cites·43 claims
- 1641US6737858B2Method and apparatus for testing current sinking/sourcing capability of a driver circuitAGILENT TECHNOLOGIES INC·Filed 2002·Granted May 18, 2004·1 cites·17 claims
- 1735US2004123194A1Systems and methods for testing tri-state bus driversFiled 2002·Application pending·0 cites
- 1835US2004123195A1Systems and methods for testing tri-state bus driversFiled 2002·Application pending·0 cites
- 1935US2004187060A1Generating test patterns for testing an integrated circuitFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →