Inventor · disambiguated record
Jeffrey Erik Schulz
Also filed as: SCHULZ JEFFREY · SCHULZ JEFFREY ERIK
26 granted patents·5 pending applications·94 citations·filing 2003–2024
94Inventor score
Top patents by PatentIndex Score
31 records- 0196US10445278B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2016·Granted Oct 15, 2019·13 cites·21 claims
- 0295US9712186B1Serial memory interface circuitry for programmable integrated circuitsALTERA CORP·Filed 2014·Granted Jul 18, 2017·18 cites·25 claims
- 0389US9077338B1Method and circuit for scalable cross point switching using 3-D die stackingALTERA CORP·Filed 2014·Granted Jul 7, 2015·10 cites·20 claims
- 0489US9032162B1Systems and methods for providing memory controllers with memory access request merging capabilitiesCHANG CHING-CHI·Filed 2011·Granted May 12, 2015·24 cites·19 claims
- 0588US2025021506A1Interface Bridge Between Integrated Circuit DieALTERA CORP·Filed 2024·Application pending·0 cites
- 0686US9735778B1Method and apparatuses for optimizing power management on an integrated circuit deviceALTERA CORP·Filed 2014·Granted Aug 15, 2017·7 cites·21 claims
- 0784US11100029B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2019·Granted Aug 24, 2021·2 cites·24 claims
- 0883US12135667B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 0977US11693810B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2021·Granted Jul 4, 2023·0 cites·20 claims
- 1075US10871906B2Periphery shoreline augmentation for integrated circuitsINTEL CORP·Filed 2018·Granted Dec 22, 2020·3 cites·20 claims
- 1175US8930641B1Systems and methods for providing memory controllers with scheduler bypassing capabilitiesKAPASI RAVISH·Filed 2011·Granted Jan 6, 2015·8 cites·18 claims
- 1273US11237998B2Interface bridge between integrated circuit dieINTEL CORP·Filed 2020·Granted Feb 1, 2022·0 cites·54 claims
- 1373US9276582B2Method and circuit for scalable cross point switching using 3-D die stackingALTERA CORP·Filed 2015·Granted Mar 1, 2016·2 cites·20 claims
- 1472US12191893B2Seemingly monolithic interface between separate integrated circuit dieINTEL CORP·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 1569US9424073B1Transaction handling between soft logic and hard logic components of a memory controllerALTERA CORP·Filed 2014·Granted Aug 23, 2016·2 cites·17 claims
- 1665US10591544B2Programmable integrated circuits with in-operation reconfiguration capabilityALTERA CORP·Filed 2018·Granted Mar 17, 2020·0 cites·20 claims
- 1763US11449247B2Periphery shoreline augmentation for integrated circuitsINTEL CORP·Filed 2020·Granted Sep 20, 2022·0 cites·20 claims
- 1862US11101930B2Serial memory interface circuitry for programmable integrated circuitsALTERA CORP·Filed 2019·Granted Aug 24, 2021·0 cites·20 claims
- 1961US11075648B2Seemingly monolithic interface between separate integrated circuit dieINTEL CORP·Filed 2019·Granted Jul 27, 2021·0 cites·20 claims
- 2061US2025125296A1Double Bump Design for Multiple Purpose IO ConnectionsKOLLURU KRISHNA BHARATH·Filed 2024·Application pending·0 cites
- 2156US10491333B2Serial memory interface circuitry for programmable integrated circuitsALTERA CORP·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 2255US10439639B2Seemingly monolithic interface between separate integrated circuit dieINTEL CORP·Filed 2016·Granted Oct 8, 2019·0 cites·21 claims
- 2355US9208109B2Memory controllers with dynamic port priority assignment capabilitiesCHU MICHAEL H M·Filed 2011·Granted Dec 8, 2015·1 cites·16 claims
- 2454US9244867B1Memory controller interface with adjustable port widthsSCHULZ JEFFREY·Filed 2011·Granted Jan 26, 2016·1 cites·21 claims
- 2551US10082541B2Mixed redundancy scheme for inter-die interconnects in a multichip packageALTERA CORP·Filed 2015·Granted Sep 25, 2018·0 cites·20 claims
- 2651US2023123826A1Source Synchronous Partition of an SDRAM Controller SubsystemINTEL CORP·Filed 2022·Application pending·0 cites
- 2749US9343124B1Method and system for operating a multi-port memory systemCHEN CAROLINE SSU-MIN·Filed 2011·Granted May 17, 2016·2 cites·25 claims
- 2849US2023140547A1Input Output Banks of a Programmable Logic DeviceINTEL CORP·Filed 2022·Application pending·0 cites
- 2946US7352751B2Accounting for link utilization in scheduling and billingERICSSON AB·Filed 2003·Granted Apr 1, 2008·1 cites·17 claims
- 3046US2023118912A1Techniques For Synchronous Accesses To Storage CircuitsINTEL CORP·Filed 2022·Application pending·0 cites
- 3142US9558131B1Integrated circuit with bonding circuits for bonding memory controllersSCHULZ JEFFREY·Filed 2011·Granted Jan 31, 2017·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →